Francois Ramu 5a51fe515a soc: arm: stm32g0 with USB-C PD cannot use CC1 and CC2 pins by default ... With this patch, the UCPD1 _CC1 and _CC2 pins are disabling the USB Type-C and Power Delivery Dead Battery. Signed-off-by: Francois Ramu <francois.ramu@st.com>		2021-04-09 14:53:57 -04:00
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arc	ARC: Kconfig: cleanup CPU_ARCEM / CPU_ARCHS options usage	2021-03-25 07:23:02 -04:00
arm	soc: arm: stm32g0 with USB-C PD cannot use CC1 and CC2 pins by default	2021-04-09 14:53:57 -04:00
arm64	soc: arm64: add NXP ls1046a support	2021-04-09 13:25:15 +02:00
nios2
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	soc: riscv: enable COMPRESSED_ISA for ITE chips	2021-03-25 07:07:19 -04:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	x86: remove CONFIG_CPU_MINUTEIA	2021-03-11 06:37:02 -05:00
xtensa	soc: intel_s1000: remove log and ztest XCC fixes	2021-03-26 11:19:52 -05:00
Kconfig	timing: introduce timing functions as a generic feature	2020-09-05 13:28:38 -05:00