Add clock driver for Intel SoC FPGA Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
17 lines
457 B
C
17 lines
457 B
C
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2021, Intel Corporation
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*
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_
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#define INTEL_SOCFPGA_CLOCK_MPU 0
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#define INTEL_SOCFPGA_CLOCK_WDT 1
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#define INTEL_SOCFPGA_CLOCK_UART 2
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#define INTEL_SOCFPGA_CLOCK_MMC 3
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_ */
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