cdd02a99a1
Since linker_final_pass.cmd is the actual linker script being used to link the final Zephyr binary, rename it to linker.cmd. This also renames LINKER_PASS2 to LINKER_ZEPHYR_FINAL simply to clarify what it is used for, instead of ambiguous pass #n. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2020 Intel Corp.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Pagetables. These are produced by arch/x86/gen-mmu.py based on
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* data in zephyr_prebuilt.elf (the result of linker pass 1).
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* For the pass 1 build, an equal-sized dummy area is provided as
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* to not shift memory addresses that occur after this.
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*/
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#ifdef CONFIG_MMU
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SECTION_DATA_PROLOGUE(pagetables,,)
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{
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. = ALIGN(4096);
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z_x86_pagetables_start = .;
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#ifdef LINKER_ZEPHYR_FINAL
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KEEP(*(pagetables)) /* gen_mmu.py */
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#else
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KEEP(*(.dummy_pagetables)) /* from x86_mmu.c, just an empty array */
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#endif /* LINKER_ZEPHYR_FINAL */
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/* Top-level paging structure is the last thing in this section */
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#if CONFIG_X86_PAE
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/* 4-entry PDPT */
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z_x86_kernel_ptables = . - 32;
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#else
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/* Page directory or PML4 */
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z_x86_kernel_ptables = . - 4096;
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#endif /* CONFIG_X86_PAE */
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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#ifdef LINKER_ZEPHYR_FINAL
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/DISCARD/ :
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{
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/* We have the real ones in this build */
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*(.dummy_pagetables)
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}
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#endif /* LINKER_ZEPHYR_FINAL */
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#endif /* CONFIG_MMU */
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