88477906f0
Let's fully exploit tpidrro_el0 by storing in it the current CPU's struct _cpu instance alongside the userspace mode flag bit. This greatly simplifies the code needed to get at the cpu structure, and this paves the way to much simpler multi cluster support, as there is no longer the need to decode MPIDR all the time. The same code is used in the !SMP case as there are benefits there too such as avoiding the literal pool, and it looks cleaner. The tpidrro_el0 value is no longer stored in the exception stack frame. Instead, we simply restore the user mode flag based on the SPSR value. This way, more flag bits could be used independently in the future. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
211 lines
6.2 KiB
C
211 lines
6.2 KiB
C
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_
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#include <sys/util.h>
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#define DAIFSET_FIQ_BIT BIT(0)
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#define DAIFSET_IRQ_BIT BIT(1)
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#define DAIFSET_ABT_BIT BIT(2)
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#define DAIFSET_DBG_BIT BIT(3)
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#define DAIFCLR_FIQ_BIT BIT(0)
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#define DAIFCLR_IRQ_BIT BIT(1)
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#define DAIFCLR_ABT_BIT BIT(2)
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#define DAIFCLR_DBG_BIT BIT(3)
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#define DAIF_FIQ_BIT BIT(6)
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#define DAIF_IRQ_BIT BIT(7)
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#define DAIF_ABT_BIT BIT(8)
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#define DAIF_DBG_BIT BIT(9)
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#define SPSR_DAIF_SHIFT (6)
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#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
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#define SPSR_MODE_EL0T (0x0)
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#define SPSR_MODE_EL1T (0x4)
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#define SPSR_MODE_EL1H (0x5)
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#define SPSR_MODE_EL2T (0x8)
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#define SPSR_MODE_EL2H (0x9)
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#define SPSR_MODE_MASK (0xf)
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#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(5) | BIT(4))
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#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(18) | BIT(16) | \
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BIT(11) | BIT(5) | BIT(4))
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#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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BIT(22) | BIT(20) | BIT(11))
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#define SCTLR_M_BIT BIT(0)
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#define SCTLR_A_BIT BIT(1)
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#define SCTLR_C_BIT BIT(2)
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#define SCTLR_SA_BIT BIT(3)
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#define SCTLR_I_BIT BIT(12)
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#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
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#define SCR_NS_BIT BIT(0)
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#define SCR_IRQ_BIT BIT(1)
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#define SCR_FIQ_BIT BIT(2)
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#define SCR_EA_BIT BIT(3)
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#define SCR_SMD_BIT BIT(7)
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#define SCR_HCE_BIT BIT(8)
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#define SCR_RW_BIT BIT(10)
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#define SCR_ST_BIT BIT(11)
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#define SCR_RES1 (BIT(4) | BIT(5))
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/* MPIDR */
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#define MPIDR_AFFLVL_MASK (0xff)
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#define MPIDR_AFF0_SHIFT (0)
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#define MPIDR_AFF1_SHIFT (8)
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#define MPIDR_AFF2_SHIFT (16)
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#define MPIDR_AFF3_SHIFT (32)
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#define MPIDR_AFFLVL(mpidr, aff_level) \
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(((mpidr) >> MPIDR_AFF##aff_level##_SHIFT) & MPIDR_AFFLVL_MASK)
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#define GET_MPIDR() read_sysreg(mpidr_el1)
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#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
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#define IS_PRIMARY_CORE() (!MPIDR_TO_CORE(GET_MPIDR()))
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#define MODE_EL_SHIFT (0x2)
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#define MODE_EL_MASK (0x3)
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#define MODE_EL3 (0x3)
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#define MODE_EL2 (0x2)
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#define MODE_EL1 (0x1)
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#define MODE_EL0 (0x0)
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#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
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#define ESR_EC_SHIFT (26)
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#define ESR_EC_MASK BIT_MASK(6)
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#define ESR_ISS_SHIFT (0)
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#define ESR_ISS_MASK BIT_MASK(25)
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#define ESR_IL_SHIFT (25)
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#define ESR_IL_MASK BIT_MASK(1)
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#define GET_ESR_EC(esr) (((esr) >> ESR_EC_SHIFT) & ESR_EC_MASK)
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#define GET_ESR_IL(esr) (((esr) >> ESR_IL_SHIFT) & ESR_IL_MASK)
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#define GET_ESR_ISS(esr) (((esr) >> ESR_ISS_SHIFT) & ESR_ISS_MASK)
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#define CNTV_CTL_ENABLE_BIT BIT(0)
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#define CNTV_CTL_IMASK_BIT BIT(1)
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#define ID_AA64PFR0_EL0_SHIFT (0)
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#define ID_AA64PFR0_EL1_SHIFT (4)
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#define ID_AA64PFR0_EL2_SHIFT (8)
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#define ID_AA64PFR0_EL3_SHIFT (12)
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#define ID_AA64PFR0_ELX_MASK (0xf)
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#define ID_AA64PFR0_SEL2_SHIFT (36)
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#define ID_AA64PFR0_SEL2_MASK (0xf)
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/*
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* TODO: ACTLR is of class implementation defined. All core implementations
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* in armv8a have the same implementation so far w.r.t few controls.
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* When there will be differences we have to create core specific headers.
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*/
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#define ACTLR_EL3_CPUACTLR_BIT BIT(0)
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#define ACTLR_EL3_CPUECTLR_BIT BIT(1)
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#define ACTLR_EL3_L2CTLR_BIT BIT(4)
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#define ACTLR_EL3_L2ECTLR_BIT BIT(5)
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#define ACTLR_EL3_L2ACTLR_BIT BIT(6)
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#define CPTR_EZ_BIT BIT(8)
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#define CPTR_TFP_BIT BIT(10)
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#define CPTR_TTA_BIT BIT(20)
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#define CPTR_TCPAC_BIT BIT(31)
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#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
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#define HCR_FMO_BIT BIT(3)
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#define HCR_IMO_BIT BIT(4)
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#define HCR_AMO_BIT BIT(5)
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#define HCR_RW_BIT BIT(31)
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/* System register interface to GICv3 */
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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#define ICC_SGI1R S3_0_C12_C11_5
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_RPR_EL1 S3_0_C12_C11_3
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#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
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#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
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#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
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#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
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#define ICC_IAR0_EL1 S3_0_C12_C8_0
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#define ICC_IAR1_EL1 S3_0_C12_C12_0
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#define ICC_EOIR0_EL1 S3_0_C12_C8_1
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#define ICC_EOIR1_EL1 S3_0_C12_C12_1
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#define ICC_SGI0R_EL1 S3_0_C12_C11_7
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/* register constants */
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#define ICC_SRE_ELx_SRE_BIT BIT(0)
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#define ICC_SRE_ELx_DFB_BIT BIT(1)
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#define ICC_SRE_ELx_DIB_BIT BIT(2)
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#define ICC_SRE_EL3_EN_BIT BIT(3)
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/* ICC SGI macros */
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#define SGIR_TGT_MASK (0xffff)
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#define SGIR_AFF1_SHIFT (16)
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#define SGIR_AFF2_SHIFT (32)
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#define SGIR_AFF3_SHIFT (48)
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#define SGIR_AFF_MASK (0xf)
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#define SGIR_INTID_SHIFT (24)
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#define SGIR_INTID_MASK (0xf)
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#define SGIR_IRM_SHIFT (40)
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#define SGIR_IRM_MASK (0x1)
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#define SGIR_IRM_TO_AFF (0)
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#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
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((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
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(((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
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(((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
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(((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
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(((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
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((_tgt) & SGIR_TGT_MASK))
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/* Implementation defined register definations */
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#if defined(CONFIG_CPU_CORTEX_A72)
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#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT (0)
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#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT (5)
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT (6)
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#define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT (9)
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES (2)
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK (0x7)
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#define CORTEX_A72_L2_DATA_RAM_SETUP_1_CYCLE (1)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES (1)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES (2)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK (0x7)
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#define CORTEX_A72_L2_TAG_RAM_SETUP_1_CYCLE (1)
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#define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT BIT(6)
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#endif /* CONFIG_CPU_CORTEX_A72 */
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#define L1_CACHE_SHIFT (6)
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#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
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#define ARM64_CPU_INIT_SIZE L1_CACHE_BYTES
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_CPU_H_ */
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