d282d86d7e
Include the new introduced include/arch/arm64/mm.h instead of the arm_mmu.h or arm_mpu.h. Unify function names z_arm64_thread_pt_init/z_arm64_swap_ptables with z_arm64_thread_mem_domains_init/z_arm64_swap_mem_domains for mmu and mpu, because: 1. mmu and mpu have almost the same logic. 2. mpu doesn't have ptables. 3. using the function names help reducing "#if define" macros. Similarly, change z_arm64_ptable_ipi to z_arm64_domain_sync_ipi And fix a log bug in arm_mmu.c. Signed-off-by: Jaxson Han <jaxson.han@arm.com>
224 lines
6.9 KiB
C
224 lines
6.9 KiB
C
/*
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* Copyright 2019 Broadcom
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* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MMU_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MMU_H_
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/* Following Memory types supported through MAIR encodings can be passed
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* by user through "attrs"(attributes) field of specified memory region.
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* As MAIR supports such 8 encodings, we will reserve attrs[2:0];
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* so that we can provide encodings upto 7 if needed in future.
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*/
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#define MT_TYPE_MASK 0x7U
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#define MT_TYPE(attr) (attr & MT_TYPE_MASK)
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#define MT_DEVICE_nGnRnE 0U
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#define MT_DEVICE_nGnRE 1U
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#define MT_DEVICE_GRE 2U
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#define MT_NORMAL_NC 3U
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#define MT_NORMAL 4U
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#define MT_NORMAL_WT 5U
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#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_nGnRnE * 8)) | \
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(0x04 << (MT_DEVICE_nGnRE * 8)) | \
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(0x0c << (MT_DEVICE_GRE * 8)) | \
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(0x44 << (MT_NORMAL_NC * 8)) | \
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(0xffUL << (MT_NORMAL * 8)) | \
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(0xbbUL << (MT_NORMAL_WT * 8)))
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/* More flags from user's perpective are supported using remaining bits
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* of "attrs" field, i.e. attrs[31:3], underlying code will take care
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* of setting PTE fields correctly.
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*
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* current usage of attrs[31:3] is:
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* attrs[3] : Access Permissions
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* attrs[4] : Memory access from secure/ns state
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* attrs[5] : Execute Permissions privileged mode (PXN)
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* attrs[6] : Execute Permissions unprivileged mode (UXN)
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* attrs[7] : Mirror RO/RW permissions to EL0
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* attrs[8] : Overwrite existing mapping if any
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*
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*/
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#define MT_PERM_SHIFT 3U
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#define MT_SEC_SHIFT 4U
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#define MT_P_EXECUTE_SHIFT 5U
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#define MT_U_EXECUTE_SHIFT 6U
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#define MT_RW_AP_SHIFT 7U
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#define MT_NO_OVERWRITE_SHIFT 8U
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#define MT_RO (0U << MT_PERM_SHIFT)
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#define MT_RW (1U << MT_PERM_SHIFT)
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#define MT_RW_AP_ELx (1U << MT_RW_AP_SHIFT)
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#define MT_RW_AP_EL_HIGHER (0U << MT_RW_AP_SHIFT)
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#define MT_SECURE (0U << MT_SEC_SHIFT)
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#define MT_NS (1U << MT_SEC_SHIFT)
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#define MT_P_EXECUTE (0U << MT_P_EXECUTE_SHIFT)
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#define MT_P_EXECUTE_NEVER (1U << MT_P_EXECUTE_SHIFT)
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#define MT_U_EXECUTE (0U << MT_U_EXECUTE_SHIFT)
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#define MT_U_EXECUTE_NEVER (1U << MT_U_EXECUTE_SHIFT)
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#define MT_NO_OVERWRITE (1U << MT_NO_OVERWRITE_SHIFT)
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#define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
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#define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
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#define MT_P_RO_U_RO (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
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#define MT_P_RO_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
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#define MT_P_RO_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE)
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#define MT_P_RX_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE | MT_U_EXECUTE)
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#define MT_P_RX_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE | MT_U_EXECUTE_NEVER)
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#ifdef CONFIG_ARMV8_A_NS
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#define MT_DEFAULT_SECURE_STATE MT_NS
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#else
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#define MT_DEFAULT_SECURE_STATE MT_SECURE
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#endif
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/*
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* PTE descriptor can be Block descriptor or Table descriptor
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* or Page descriptor.
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*/
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#define PTE_DESC_TYPE_MASK 3U
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#define PTE_BLOCK_DESC 1U
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#define PTE_TABLE_DESC 3U
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#define PTE_PAGE_DESC 3U
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#define PTE_INVALID_DESC 0U
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/*
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* Block and Page descriptor attributes fields
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*/
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#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2)
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#define PTE_BLOCK_DESC_NS (1ULL << 5)
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#define PTE_BLOCK_DESC_AP_ELx (1ULL << 6)
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#define PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6)
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#define PTE_BLOCK_DESC_AP_RO (1ULL << 7)
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#define PTE_BLOCK_DESC_AP_RW (0ULL << 7)
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#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8)
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#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8)
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#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8)
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#define PTE_BLOCK_DESC_AF (1ULL << 10)
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#define PTE_BLOCK_DESC_NG (1ULL << 11)
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#define PTE_BLOCK_DESC_PXN (1ULL << 53)
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#define PTE_BLOCK_DESC_UXN (1ULL << 54)
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/*
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* TCR definitions.
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*/
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#define TCR_EL1_IPS_SHIFT 32U
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#define TCR_EL2_PS_SHIFT 16U
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#define TCR_EL3_PS_SHIFT 16U
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#define TCR_T0SZ_SHIFT 0U
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#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT)
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#define TCR_IRGN_NC (0ULL << 8)
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#define TCR_IRGN_WBWA (1ULL << 8)
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#define TCR_IRGN_WT (2ULL << 8)
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#define TCR_IRGN_WBNWA (3ULL << 8)
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#define TCR_IRGN_MASK (3ULL << 8)
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#define TCR_ORGN_NC (0ULL << 10)
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#define TCR_ORGN_WBWA (1ULL << 10)
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#define TCR_ORGN_WT (2ULL << 10)
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#define TCR_ORGN_WBNWA (3ULL << 10)
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#define TCR_ORGN_MASK (3ULL << 10)
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#define TCR_SHARED_NON (0ULL << 12)
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#define TCR_SHARED_OUTER (2ULL << 12)
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#define TCR_SHARED_INNER (3ULL << 12)
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#define TCR_TG0_4K (0ULL << 14)
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#define TCR_TG0_64K (1ULL << 14)
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#define TCR_TG0_16K (2ULL << 14)
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#define TCR_EPD1_DISABLE (1ULL << 23)
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#define TCR_PS_BITS_4GB 0x0ULL
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#define TCR_PS_BITS_64GB 0x1ULL
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#define TCR_PS_BITS_1TB 0x2ULL
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#define TCR_PS_BITS_4TB 0x3ULL
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#define TCR_PS_BITS_16TB 0x4ULL
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#define TCR_PS_BITS_256TB 0x5ULL
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#ifndef _ASMLANGUAGE
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/* Region definition data structure */
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struct arm_mmu_region {
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/* Region Base Physical Address */
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uintptr_t base_pa;
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/* Region Base Virtual Address */
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uintptr_t base_va;
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/* Region size */
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size_t size;
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/* Region Name */
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const char *name;
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/* Region Attributes */
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uint32_t attrs;
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};
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/* MMU configuration data structure */
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struct arm_mmu_config {
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/* Number of regions */
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unsigned int num_regions;
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/* Regions */
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const struct arm_mmu_region *mmu_regions;
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};
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struct arm_mmu_ptables {
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uint64_t *base_xlat_table;
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};
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/* Convenience macros to represent the ARMv8-A-specific
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* configuration for memory access permission and
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* cache-ability attribution.
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*/
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#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \
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{\
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.name = _name, \
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.base_pa = _base_pa, \
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.base_va = _base_va, \
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.size = _size, \
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.attrs = _attrs, \
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}
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#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \
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MMU_REGION_ENTRY(name, adr, adr, sz, attrs)
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/* Kernel macros for memory attribution
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* (access permissions and cache-ability).
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*
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* The macros are to be stored in k_mem_partition_attr_t
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* objects. The format of a k_mem_partition_attr_t object
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* is an uint32_t composed by permission and attribute flags
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* located in include/arch/arm64/arm_mmu.h
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*/
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/* Read-Write access permission attributes */
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#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \
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{MT_P_RW_U_RW})
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#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \
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{MT_P_RW_U_NA})
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#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \
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{MT_P_RO_U_RO})
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#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \
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{MT_P_RO_U_NA})
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/* Execution-allowed attributes */
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#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \
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{MT_P_RX_U_RX})
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/* Typedef for the k_mem_partition attribute */
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typedef struct { uint32_t attrs; } k_mem_partition_attr_t;
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/* Reference to the MMU configuration.
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*
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* This struct is defined and populated for each SoC (in the SoC definition),
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* and holds the build-time configuration information for the fixed MMU
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* regions enabled during kernel initialization.
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*/
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extern const struct arm_mmu_config mmu_config;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_ARM_MMU_H_ */
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