f70ecc1099
So far pcie_get_mbar() has been the only way to retrieve a MBAR. But it's logic does not fit all uses cases as we will see further. The meaning of its parameter "index" is not about BAR index but about a valid Base Address count instead. It's an arbitrary way to index MBARs unrelated to the actual BAR index. While this has proven to be just the function we needed so far, this has not been the case for MSI-X, which one (through BIR info) needs to access the BAR by their actual index. Same as ivshmem in fact, though that one did not generate any bug since it never has IO BARs nor 64bits BARs (so far?). So: - renaming existing pcie_get_mbar() to pcie_probe_mbar(), which is a more relevant name as it indeed probes the BARs to find the nth valid one. - Introducing a new pcie_get_mbar() which this time really asks for the BAR index. - Applying the change where relevant. So all use pcie_probe_mbar() now but MSI-X and ivshmem. Fixes #37444 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
459 lines
9.4 KiB
C
459 lines
9.4 KiB
C
/*
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* Copyright (c) 2018-2019 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_e1000
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#define LOG_MODULE_NAME eth_e1000
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include <sys/types.h>
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#include <zephyr.h>
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#include <net/ethernet.h>
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#include <ethernet/eth_stats.h>
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#include <drivers/pcie/pcie.h>
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#include "eth_e1000_priv.h"
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#if defined(CONFIG_ETH_E1000_PTP_CLOCK)
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#include <ptp_clock.h>
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#define PTP_INST_NODEID(n) DT_CHILD(DT_DRV_INST(n), ptp)
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#endif
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#if defined(CONFIG_ETH_E1000_VERBOSE_DEBUG)
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#define hexdump(_buf, _len, fmt, args...) \
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({ \
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const size_t STR_SIZE = 80; \
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char _str[STR_SIZE]; \
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\
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snprintk(_str, STR_SIZE, "%s: " fmt, __func__, ## args); \
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\
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LOG_HEXDUMP_DBG(_buf, _len, log_strdup(_str)); \
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})
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#else
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#define hexdump(args...)
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#endif
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static const char *e1000_reg_to_string(enum e1000_reg_t r)
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{
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#define _(_x) case _x: return #_x
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switch (r) {
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_(CTRL);
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_(ICR);
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_(ICS);
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_(IMS);
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_(RCTL);
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_(TCTL);
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_(RDBAL);
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_(RDBAH);
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_(RDLEN);
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_(RDH);
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_(RDT);
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_(TDBAL);
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_(TDBAH);
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_(TDLEN);
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_(TDH);
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_(TDT);
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_(RAL);
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_(RAH);
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}
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#undef _
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LOG_ERR("Unsupported register: 0x%x", r);
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k_oops();
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return NULL;
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}
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static struct net_if *get_iface(struct e1000_dev *ctx, uint16_t vlan_tag)
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{
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#if defined(CONFIG_NET_VLAN)
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struct net_if *iface;
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iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag);
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if (!iface) {
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return ctx->iface;
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}
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return iface;
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#else
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ARG_UNUSED(vlan_tag);
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return ctx->iface;
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#endif
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}
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static enum ethernet_hw_caps e1000_caps(const struct device *dev)
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{
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return
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#if IS_ENABLED(CONFIG_NET_VLAN)
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ETHERNET_HW_VLAN |
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#endif
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#if IS_ENABLED(CONFIG_ETH_E1000_PTP_CLOCK)
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ETHERNET_PTP |
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#endif
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ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T |
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ETHERNET_LINK_1000BASE_T |
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/* The driver does not really support TXTIME atm but mark
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* it to support it so that we can test the txtime sample.
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*/
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ETHERNET_TXTIME;
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}
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#if defined(CONFIG_ETH_E1000_PTP_CLOCK)
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static const struct device *e1000_get_ptp_clock(const struct device *dev)
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{
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struct e1000_dev *ctx = dev->data;
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return ctx->ptp_clock;
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}
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#endif
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static int e1000_tx(struct e1000_dev *dev, void *buf, size_t len)
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{
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hexdump(buf, len, "%zu byte(s)", len);
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dev->tx.addr = POINTER_TO_INT(buf);
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dev->tx.len = len;
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dev->tx.cmd = TDESC_EOP | TDESC_RS;
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iow32(dev, TDT, 1);
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while (!(dev->tx.sta)) {
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k_yield();
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}
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LOG_DBG("tx.sta: 0x%02hx", dev->tx.sta);
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return (dev->tx.sta & TDESC_STA_DD) ? 0 : -EIO;
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}
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static int e1000_send(const struct device *ddev, struct net_pkt *pkt)
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{
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struct e1000_dev *dev = ddev->data;
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size_t len = net_pkt_get_len(pkt);
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if (net_pkt_read(pkt, dev->txb, len)) {
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return -EIO;
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}
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return e1000_tx(dev, dev->txb, len);
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}
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static struct net_pkt *e1000_rx(struct e1000_dev *dev)
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{
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struct net_pkt *pkt = NULL;
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void *buf;
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ssize_t len;
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LOG_DBG("rx.sta: 0x%02hx", dev->rx.sta);
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if (!(dev->rx.sta & RDESC_STA_DD)) {
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LOG_ERR("RX descriptor not ready");
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goto out;
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}
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buf = INT_TO_POINTER((uint32_t)dev->rx.addr);
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len = dev->rx.len - 4;
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if (len <= 0) {
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LOG_ERR("Invalid RX descriptor length: %hu", dev->rx.len);
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goto out;
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}
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hexdump(buf, len, "%zd byte(s)", len);
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pkt = net_pkt_rx_alloc_with_buffer(dev->iface, len, AF_UNSPEC, 0,
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K_NO_WAIT);
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if (!pkt) {
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LOG_ERR("Out of buffers");
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goto out;
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}
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if (net_pkt_write(pkt, buf, len)) {
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LOG_ERR("Out of memory for received frame");
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net_pkt_unref(pkt);
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pkt = NULL;
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}
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out:
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return pkt;
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}
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static void e1000_isr(const struct device *ddev)
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{
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struct e1000_dev *dev = ddev->data;
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uint32_t icr = ior32(dev, ICR); /* Cleared upon read */
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uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC;
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icr &= ~(ICR_TXDW | ICR_TXQE);
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if (icr & ICR_RXO) {
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struct net_pkt *pkt = e1000_rx(dev);
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icr &= ~ICR_RXO;
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if (pkt) {
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#if defined(CONFIG_NET_VLAN)
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struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
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if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) {
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struct net_eth_vlan_hdr *hdr_vlan =
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(struct net_eth_vlan_hdr *)
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NET_ETH_HDR(pkt);
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net_pkt_set_vlan_tci(
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pkt, ntohs(hdr_vlan->vlan.tci));
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vlan_tag = net_pkt_vlan_tag(pkt);
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#if CONFIG_NET_TC_RX_COUNT > 1
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enum net_priority prio;
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prio = net_vlan2priority(
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net_pkt_vlan_priority(pkt));
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net_pkt_set_priority(pkt, prio);
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#endif
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}
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#endif /* CONFIG_NET_VLAN */
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net_recv_data(get_iface(dev, vlan_tag), pkt);
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} else {
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eth_stats_update_errors_rx(get_iface(dev, vlan_tag));
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}
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}
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if (icr) {
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LOG_ERR("Unhandled interrupt, ICR: 0x%x", icr);
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}
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}
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_I82540EM 0x100e
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int e1000_probe(const struct device *ddev)
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{
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const pcie_bdf_t bdf = PCIE_BDF(0, 3, 0);
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struct e1000_dev *dev = ddev->data;
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uint32_t ral, rah;
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struct pcie_mbar mbar;
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if (!pcie_probe(bdf, PCIE_ID(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_I82540EM))) {
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return -ENODEV;
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}
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pcie_probe_mbar(bdf, 0, &mbar);
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pcie_set_cmd(bdf, PCIE_CONF_CMDSTAT_MEM |
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PCIE_CONF_CMDSTAT_MASTER, true);
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device_map(&dev->address, mbar.phys_addr, mbar.size,
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K_MEM_CACHE_NONE);
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/* Setup TX descriptor */
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iow32(dev, TDBAL, (uint32_t) &dev->tx);
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iow32(dev, TDBAH, 0);
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iow32(dev, TDLEN, 1*16);
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iow32(dev, TDH, 0);
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iow32(dev, TDT, 0);
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iow32(dev, TCTL, TCTL_EN);
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/* Setup RX descriptor */
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dev->rx.addr = POINTER_TO_INT(dev->rxb);
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dev->rx.len = sizeof(dev->rxb);
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iow32(dev, RDBAL, (uint32_t) &dev->rx);
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iow32(dev, RDBAH, 0);
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iow32(dev, RDLEN, 1*16);
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iow32(dev, RDH, 0);
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iow32(dev, RDT, 1);
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iow32(dev, IMS, IMS_RXO);
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ral = ior32(dev, RAL);
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rah = ior32(dev, RAH);
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memcpy(dev->mac, &ral, 4);
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memcpy(dev->mac + 4, &rah, 2);
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return 0;
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}
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static void e1000_iface_init(struct net_if *iface)
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{
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struct e1000_dev *dev = net_if_get_device(iface)->data;
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/* For VLAN, this value is only used to get the correct L2 driver.
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* The iface pointer in device context should contain the main
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* interface if the VLANs are enabled.
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*/
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if (dev->iface == NULL) {
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dev->iface = iface;
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/* Do the phy link up only once */
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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e1000_isr, DEVICE_DT_INST_GET(0),
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DT_INST_IRQ(0, sense));
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irq_enable(DT_INST_IRQN(0));
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iow32(dev, CTRL, CTRL_SLU); /* Set link up */
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iow32(dev, RCTL, RCTL_EN | RCTL_MPE);
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}
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ethernet_init(iface);
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net_if_set_link_addr(iface, dev->mac, sizeof(dev->mac),
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NET_LINK_ETHERNET);
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LOG_DBG("done");
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}
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static struct e1000_dev e1000_dev;
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static const struct ethernet_api e1000_api = {
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.iface_api.init = e1000_iface_init,
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#if defined(CONFIG_ETH_E1000_PTP_CLOCK)
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.get_ptp_clock = e1000_get_ptp_clock,
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#endif
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.get_capabilities = e1000_caps,
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.send = e1000_send,
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};
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ETH_NET_DEVICE_DT_INST_DEFINE(0,
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e1000_probe,
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NULL,
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&e1000_dev,
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NULL,
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CONFIG_ETH_INIT_PRIORITY,
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&e1000_api,
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NET_ETH_MTU);
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#if defined(CONFIG_ETH_E1000_PTP_CLOCK)
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struct ptp_context {
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struct e1000_dev *eth_context;
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/* Simulate the clock. This is only for testing.
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* The value is in nanoseconds
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*/
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uint64_t clock_time;
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};
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static struct ptp_context ptp_e1000_context;
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static int ptp_clock_e1000_set(const struct device *dev,
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struct net_ptp_time *tm)
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{
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struct ptp_context *ptp_context = dev->data;
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/* TODO: Set the clock real value here */
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ptp_context->clock_time = tm->second * NSEC_PER_SEC + tm->nanosecond;
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return 0;
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}
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static int ptp_clock_e1000_get(const struct device *dev,
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struct net_ptp_time *tm)
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{
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struct ptp_context *ptp_context = dev->data;
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/* TODO: Get the clock value */
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tm->second = ptp_context->clock_time / NSEC_PER_SEC;
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tm->nanosecond = ptp_context->clock_time - tm->second * NSEC_PER_SEC;
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return 0;
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}
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static int ptp_clock_e1000_adjust(const struct device *dev, int increment)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(increment);
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/* TODO: Implement clock adjustment */
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return 0;
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}
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static int ptp_clock_e1000_rate_adjust(const struct device *dev, float ratio)
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{
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const int hw_inc = NSEC_PER_SEC / CONFIG_ETH_E1000_PTP_CLOCK_SRC_HZ;
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struct ptp_context *ptp_context = dev->data;
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struct e1000_dev *context = ptp_context->eth_context;
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int corr;
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int32_t mul;
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float val;
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/* No change needed. */
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if (ratio == 1.0) {
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return 0;
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}
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ratio *= context->clk_ratio;
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/* Limit possible ratio. */
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if ((ratio > 1.0 + 1.0/(2 * hw_inc)) ||
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(ratio < 1.0 - 1.0/(2 * hw_inc))) {
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return -EINVAL;
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}
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/* Save new ratio. */
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context->clk_ratio = ratio;
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if (ratio < 1.0) {
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corr = hw_inc - 1;
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val = 1.0 / (hw_inc * (1.0 - ratio));
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} else if (ratio > 1.0) {
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corr = hw_inc + 1;
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val = 1.0 / (hw_inc * (ratio-1.0));
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} else {
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val = 0;
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corr = hw_inc;
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}
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if (val >= INT32_MAX) {
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/* Value is too high.
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* It is not possible to adjust the rate of the clock.
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*/
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mul = 0;
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} else {
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mul = val;
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}
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/* TODO: Adjust the clock here */
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return 0;
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}
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static const struct ptp_clock_driver_api api = {
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.set = ptp_clock_e1000_set,
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.get = ptp_clock_e1000_get,
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.adjust = ptp_clock_e1000_adjust,
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.rate_adjust = ptp_clock_e1000_rate_adjust,
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};
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static int ptp_e1000_init(const struct device *port)
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{
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const struct device *eth_dev = DEVICE_DT_INST_GET(0);
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struct e1000_dev *context = eth_dev->data;
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struct ptp_context *ptp_context = port->data;
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context->ptp_clock = port;
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ptp_context->eth_context = context;
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ptp_context->clock_time = k_ticks_to_ns_floor64(k_uptime_ticks());
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return 0;
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}
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DEVICE_DEFINE(e1000_ptp_clock, PTP_CLOCK_NAME, ptp_e1000_init,
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NULL, &ptp_e1000_context, NULL, POST_KERNEL,
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CONFIG_APPLICATION_INIT_PRIORITY, &api);
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#endif /* CONFIG_ETH_E1000_PTP_CLOCK */
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