Lixin Guo 074bd00bcb soc: intel_adsp: Change loop time in adsplog.py ... When build and run the tests manually with west, we could build successfully, but can not get output after flashing. It should rely on adsplog.py to get output, and the cause is loop time too short to get output. So, we change the loop time back to 1. Signed-off-by: Lixin Guo <lixinx.guo@intel.com>		2021-10-22 18:09:15 -04:00
..
esp32	drivers: gpio: esp32: use dts and improve code checks	2021-10-21 10:53:34 -04:00
esp32s2_saola	drivers: gpio: esp32: use dts and improve code checks	2021-10-21 10:53:34 -04:00
intel_adsp_cavs15	soc: intel_adsp: Change loop time in adsplog.py	2021-10-22 18:09:15 -04:00
intel_adsp_cavs18	intel_cavs: do not produce bin files	2021-05-07 12:35:46 -05:00
intel_adsp_cavs20	intel_cavs: do not produce bin files	2021-05-07 12:35:46 -05:00
intel_adsp_cavs25	boards/intel_adsp_cavs25: Add board documentation	2021-09-03 07:19:34 -04:00
intel_s1000_crb	interrupt_controller: remove CONFIG_DW_ICTL_OFFSET	2021-10-06 19:43:48 -04:00
nxp_adsp_imx8	boards: xtensa: adsp: select XTENSA_SMALL_VECTOR_TABLE_ENTRY for imx8 board	2021-09-10 10:59:44 -04:00
nxp_adsp_imx8m	boards: xtensa: adsp: add support for imx8m board	2021-10-20 19:08:50 -04:00
nxp_adsp_imx8x	boards: xtensa: adsp: add support for imx8x board	2021-09-27 21:52:31 -04:00
odroid_go
qemu_xtensa	dts: use 'cdns' instead of 'xtensa' vendor prefix	2021-08-17 17:51:57 -04:00
xt-sim	dts: use 'cdns' instead of 'xtensa' vendor prefix	2021-08-17 17:51:57 -04:00
index.rst