8048b14135
ARCv3 64 bit processors doesn't have Zero Delay Loop (also named Zero Overhead Loop, ZOL) mechanism. Add kconfig option to remove ZOL register save/restore so the code can be build for both ARCv2 and ARCv3. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
176 lines
3.4 KiB
C
176 lines
3.4 KiB
C
/*
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* Copyright (c) 2014-2016 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Private kernel definitions
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*
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* This file contains private kernel structures definitions and various
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* other definitions for the ARCv2 processor architecture.
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*
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* This file is also included by assembly language files which must #define
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* _ASMLANGUAGE before including this header file. Note that kernel
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* assembly source files obtains structure offset values via "absolute
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* symbols" in the offsets.o module.
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*/
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#ifndef ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_DATA_H_
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#define ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_DATA_H_
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <vector_table.h>
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#ifndef _ASMLANGUAGE
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#include <kernel.h>
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#include <zephyr/types.h>
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#include <sys/util.h>
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#include <sys/dlist.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef CONFIG_ARC_HAS_SECURE
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struct _irq_stack_frame {
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#ifdef CONFIG_ARC_HAS_ZOL
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uintptr_t lp_end;
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uintptr_t lp_start;
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uintptr_t lp_count;
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#endif /* CONFIG_ARC_HAS_ZOL */
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#ifdef CONFIG_CODE_DENSITY
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/*
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* Currently unsupported. This is where those registers are
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* automatically pushed on the stack by the CPU when taking a regular
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* IRQ.
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*/
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uintptr_t ei_base;
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uintptr_t ldi_base;
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uintptr_t jli_base;
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#endif
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uintptr_t r0;
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uintptr_t r1;
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uintptr_t r2;
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uintptr_t r3;
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uintptr_t r4;
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uintptr_t r5;
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uintptr_t r6;
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uintptr_t r7;
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uintptr_t r8;
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uintptr_t r9;
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uintptr_t r10;
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uintptr_t r11;
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uintptr_t r12;
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uintptr_t r13;
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uintptr_t blink;
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uintptr_t pc;
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uintptr_t sec_stat;
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uintptr_t status32;
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};
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#else
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struct _irq_stack_frame {
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uintptr_t r0;
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uintptr_t r1;
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uintptr_t r2;
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uintptr_t r3;
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uintptr_t r4;
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uintptr_t r5;
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uintptr_t r6;
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uintptr_t r7;
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uintptr_t r8;
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uintptr_t r9;
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uintptr_t r10;
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uintptr_t r11;
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uintptr_t r12;
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uintptr_t r13;
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uintptr_t blink;
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#ifdef CONFIG_ARC_HAS_ZOL
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uintptr_t lp_end;
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uintptr_t lp_start;
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uintptr_t lp_count;
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#endif /* CONFIG_ARC_HAS_ZOL */
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#ifdef CONFIG_CODE_DENSITY
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/*
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* Currently unsupported. This is where those registers are
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* automatically pushed on the stack by the CPU when taking a regular
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* IRQ.
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*/
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uintptr_t ei_base;
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uintptr_t ldi_base;
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uintptr_t jli_base;
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#endif
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uintptr_t pc;
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uintptr_t status32;
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};
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#endif
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typedef struct _irq_stack_frame _isf_t;
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/* callee-saved registers pushed on the stack, not in k_thread */
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struct _callee_saved_stack {
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uintptr_t r13;
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uintptr_t r14;
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uintptr_t r15;
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uintptr_t r16;
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uintptr_t r17;
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uintptr_t r18;
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uintptr_t r19;
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uintptr_t r20;
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uintptr_t r21;
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uintptr_t r22;
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uintptr_t r23;
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uintptr_t r24;
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uintptr_t r25;
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uintptr_t r26;
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uintptr_t fp; /* r27 */
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#ifdef CONFIG_USERSPACE
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#ifdef CONFIG_ARC_HAS_SECURE
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uintptr_t user_sp;
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uintptr_t kernel_sp;
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#else
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uintptr_t user_sp;
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#endif
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#endif
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/* r28 is the stack pointer and saved separately */
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/* r29 is ILINK and does not need to be saved */
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uintptr_t r30;
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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uintptr_t r58;
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uintptr_t r59;
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#endif
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#ifdef CONFIG_FPU_SHARING
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uintptr_t fpu_status;
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uintptr_t fpu_ctrl;
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#ifdef CONFIG_FP_FPU_DA
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uintptr_t dpfp2h;
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uintptr_t dpfp2l;
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uintptr_t dpfp1h;
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uintptr_t dpfp1l;
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#endif
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#endif
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/*
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* No need to save r31 (blink), it's either alread pushed as the pc or
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* blink on an irq stack frame.
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*/
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};
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typedef struct _callee_saved_stack _callee_saved_stack_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_ARC_INCLUDE_KERNEL_ARCH_DATA_H_ */
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