zephyr/tests/subsys/llext
Eric Ackermann 7293f59a05 tests: llext: Test RISC-V non-paired relocation
Tests an edge case in the RISC-V PSABI: In the medany and the medlow code
models, the compiler emits auipc/lui (U-type) and ld/sw (I-type/S-type)
instruction pairs for accessing a non-local symbol.
The U-type instruction sets the upper 20 bits, the I/S-type the lower 12.
The U-type and I-type/S-type instruction pairs are often adjacent in code.
This is also what the current llext architecture-specific relocations
expect.
However, this need not be the case - compilers can re-use the upper 20
bits set by the U-type instruction with multiple I/S-type instructions,
which is a useful optimization for multiple loads/stores of or within
the same symbol.
This commit adds a unit test for this behavior, which currently fails
for RISC-V.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2025-03-07 19:44:54 +01:00
..
boards llext: Remove simple from llext test 2025-01-02 09:19:35 +01:00
src tests: llext: Test RISC-V non-paired relocation 2025-03-07 19:44:54 +01:00
CMakeLists.txt tests: llext: Test RISC-V non-paired relocation 2025-03-07 19:44:54 +01:00
no_mem_protection.conf llext: Remove simple from llext test 2025-01-02 09:19:35 +01:00
prj.conf llext: Remove simple from llext test 2025-01-02 09:19:35 +01:00
testcase.yaml tests: subsys: llext: filter by ram/rom size 2025-02-05 21:02:33 +01:00