Eric Ackermann b7e9b2785f llext: Support non-paired RISC-V PCREL Relocation ... Currently, RISC-V's architecture-specific relocations assume that all relocations of type R_RISCV_PCREL_LO12_I and _S are processed immediately after the R_RISCV_PCREL_HI20 relocation that they share a relocation target with. While this is the case most of the time, the RISC-V PSABI specification does not guarantee that. This commit corrects this by determining the R_RISCV_PCREL_HI20 relocation based on the symbol value of the R_RISCV_PCREL_LO12 relocation, as specified in the PSABI. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>		2025-03-07 19:44:54 +01:00
..
core	llext: Support non-paired RISC-V PCREL Relocation	2025-03-07 19:44:54 +01:00
include	init: support per-core init hook	2024-11-16 14:04:25 -05:00
CMakeLists.txt
Kconfig	arch: riscv: handle interrupt level for CLIC	2025-02-05 17:48:45 +01:00
Kconfig.isa	arch/riscv: add Zaamo and Zlrsc extension subsets	2025-02-05 17:49:13 +01:00