0325a3d972
The MVIC is no longer supported, and only the APIC-based interrupt subsystem remains. Thus this layer of indirection is unnecessary. This also corrects an oversight left over from the Jailhouse x2APIC implementation affecting EOI delivery for direct ISRs only. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
47 lines
1.0 KiB
C
47 lines
1.0 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_
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#define ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_
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#include <drivers/interrupt_controller/loapic.h>
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#define IRQ_TRIGGER_EDGE IOAPIC_EDGE
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#define IRQ_TRIGGER_LEVEL IOAPIC_LEVEL
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#define IRQ_POLARITY_HIGH IOAPIC_HIGH
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#define IRQ_POLARITY_LOW IOAPIC_LOW
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#define LOAPIC_IRQ_BASE CONFIG_IOAPIC_NUM_RTES
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#define LOAPIC_IRQ_COUNT 6 /* Default to LOAPIC_TIMER to LOAPIC_ERROR */
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void z_irq_controller_irq_config(unsigned int vector, unsigned int irq,
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u32_t flags);
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int z_irq_controller_isr_vector_get(void);
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#ifdef CONFIG_X2APIC
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void z_x2apic_eoi(void);
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#endif
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static inline void z_irq_controller_eoi(void)
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{
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#if defined(CONFIG_EOI_FORWARDING_BUG)
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z_lakemont_eoi();
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#elif defined(CONFIG_X2APIC)
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z_x2apic_eoi();
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#else /* xAPIC */
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
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#endif
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}
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_DRIVERS_SYSAPIC_H_ */
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