88808f1247
Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> |
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| .. | ||
| arcv2_irq_unit.c | ||
| i8259.c | ||
| ioapic_intr.c | ||
| ioapic_priv.h | ||
| Kconfig | ||
| loapic_intr.c | ||
| loapic_spurious.S | ||
| Makefile | ||
| mvic.c | ||
| system_apic.c | ||