zephyr/include/arch
Jean-Paul Etienne 4ae030c7b8 riscv32: added support for the SiFive Freedom E310 SOC
The SiFive Freedom E310 SOC follows the riscv privilege
architecture specification and hence is declared within
the riscv privilege SOC family.

It also provides support for a riscv
Platform Level Interrupt Controller (PLIC)

Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-04-02 15:15:07 +00:00
..
arc Revert "sys_bitfield*(): use 'void *' instead of memaddr_t" 2017-02-28 16:06:22 -05:00
arm arm: cortex-m: allow configurable ROM offset 2017-02-22 18:08:57 -06:00
nios2 Revert "sys_bitfield*(): use 'void *' instead of memaddr_t" 2017-02-28 16:06:22 -05:00
riscv32 riscv32: added support for the SiFive Freedom E310 SOC 2017-04-02 15:15:07 +00:00
x86 Revert "sys_bitfield*(): use 'void *' instead of memaddr_t" 2017-02-28 16:06:22 -05:00
xtensa kernel: add flexibility to k_cycle_get_32() definition 2017-02-16 19:27:59 +00:00
cpu.h Xtensa port: Added support in arch/cpu.h for Xtensa cores. 2017-02-13 08:04:27 -08:00