08a2ca5b9b
According to the clic specification (https://github.com/riscv/riscv-fast-interrupt), the mnxti register has be written, in order to clear the pending bit for non-vectored interrupts. For vectored interrupts, this is automatically done. From the spec: "If the pending interrupt is edge-triggered, hardware will automatically clear the corresponding pending bit when the CSR instruction that accesses xnxti includes a write." I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented. For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that handles the pending interrupts according to the pseudo code in the spec. Signed-off-by: Greter Raffael <rgreter@baumer.com>
55 lines
3.3 KiB
CMake
55 lines
3.3 KiB
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_property(ALLOW_EMPTY TRUE)
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zephyr_library_sources_ifdef(CONFIG_ARCV2_INTERRUPT_UNIT intc_arcv2_irq_unit.c)
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zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL intc_cavs.c)
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zephyr_library_sources_ifdef(CONFIG_DW_ICTL intc_dw.c)
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zephyr_library_sources_ifdef(CONFIG_DW_ICTL_ACE intc_dw_ace.c)
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zephyr_library_sources_ifdef(CONFIG_EXTI_STM32 intc_exti_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_GD32_EXTI intc_gd32_exti.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V1 intc_gic.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V2 intc_gic.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V3 intc_gicv3.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS intc_gicv3_its.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c)
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zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC intc_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC_V2 intc_ite_it8xxx2_v2.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_WUC wuc_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_LEON_IRQMP intc_irqmp.c)
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zephyr_library_sources_ifdef(CONFIG_LOAPIC intc_loapic.c intc_system_apic.c)
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zephyr_library_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR intc_loapic_spurious.S)
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zephyr_library_sources_ifdef(CONFIG_MCHP_ECIA_XEC intc_mchp_ecia_xec.c)
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zephyr_library_sources_ifdef(CONFIG_NPCX_MIWU intc_miwu.c)
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zephyr_library_sources_ifdef(CONFIG_PLIC intc_plic.c)
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zephyr_library_sources_ifdef(CONFIG_RV32M1_INTMUX intc_rv32m1_intmux.c)
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zephyr_library_sources_ifdef(CONFIG_SAM0_EIC intc_sam0_eic.c)
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zephyr_library_sources_ifdef(CONFIG_SHARED_IRQ intc_shared_irq.c)
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zephyr_library_sources_ifdef(CONFIG_INTC_ESP32 intc_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3 intc_esp32c3.c)
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zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
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zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_library_sources_ifdef(CONFIG_VIM intc_vim.c)
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zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c)
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zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.S)
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zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_S32_WKPU intc_wkpu_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC intc_xmc4xxx.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_PINT intc_nxp_pint.c)
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zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_ICU intc_ra_icu.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_IRQSTEER intc_nxp_irqsteer.c)
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if(CONFIG_INTEL_VTD_ICTL)
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zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)
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endif()
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if(CONFIG_PLIC_SHELL)
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message(WARNING "
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WARNING: `CONFIG_PLIC_SHELL` is enabled.
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This can use quite a bit of RAM (PLICs * IRQs * sizeof(uint16_t))"
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)
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endif()
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zephyr_library_include_directories(${ZEPHYR_BASE}/arch/common/include)
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