8246d88bd3
Clarify a few restrictions that seem obvious but weren't specified: + On MP systems, counters are often asynchronous between cores, so you need to make sure all the values read are on the same CPU. + Many platforms have a 32 bit (or smaller, c.f. Cortex M SysTick) internal counter, but are being forced to return a 64 bit quantity that will behave badly on rollover (you can't just subtract two times anymore!). Demand that the existing arch_timing_cycles_get() API (which didn't seem to have useful much to do) implement rollover correction on the subtraction. This allows an Xtensa implementation based on direct CCOUNT reads on intel_adsp to be correct per the API docs. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| zephyr | ||