20202902f2
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/*
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* Copyright (c) 2017 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief CMSIS interface file
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*
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* This header contains the interface to the ARM CMSIS Core headers.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_CMSIS_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_CMSIS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <soc.h>
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/* CP10 Access Bits */
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#define CPACR_CP10_Pos 20U
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#define CPACR_CP10_Msk (3UL << CPACR_CP10_Pos)
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#define CPACR_CP10_NO_ACCESS (0UL << CPACR_CP10_Pos)
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#define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos)
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#define CPACR_CP10_RESERVED (2UL << CPACR_CP10_Pos)
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#define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos)
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/* CP11 Access Bits */
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#define CPACR_CP11_Pos 22U
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#define CPACR_CP11_Msk (3UL << CPACR_CP11_Pos)
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#define CPACR_CP11_NO_ACCESS (0UL << CPACR_CP11_Pos)
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#define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos)
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#define CPACR_CP11_RESERVED (2UL << CPACR_CP11_Pos)
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#define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
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#define SCB_UFSR (*((__IOM u16_t *) &SCB->CFSR + 1))
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#define SCB_BFSR (*((__IOM u8_t *) &SCB->CFSR + 1))
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#define SCB_MMFSR (*((__IOM u8_t *) &SCB->CFSR))
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/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
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* Use __NVIC_PRIO_BITS as it is required and simple to check, but
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* ultimately all SoCs will define their own CMSIS types and constants.
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*/
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#ifndef __NVIC_PRIO_BITS
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typedef enum {
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Reset_IRQn = -15,
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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SecureFault_IRQn = -9,
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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} IRQn_Type;
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#if defined(CONFIG_CPU_CORTEX_M0)
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#define __CM0_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
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#define __CM0PLUS_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M3)
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#define __CM3_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M4)
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#define __CM4_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M7)
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#define __CM7_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M23)
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#define __CM23_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M33)
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#define __CM33_REV 0
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#else
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#error "Unknown Cortex-M device"
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#endif
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#ifndef __MPU_PRESENT
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#define __MPU_PRESENT 0U
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#endif
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#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
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#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
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#endif /* __NVIC_PRIO_BITS */
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#if __NVIC_PRIO_BITS != DT_NUM_IRQ_PRIO_BITS
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#error "DT_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value"
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#endif
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#if defined(CONFIG_CPU_CORTEX_M0)
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#include <core_cm0.h>
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#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
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#include <core_cm0plus.h>
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#elif defined(CONFIG_CPU_CORTEX_M3)
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#include <core_cm3.h>
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#elif defined(CONFIG_CPU_CORTEX_M4)
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#include <core_cm4.h>
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#elif defined(CONFIG_CPU_CORTEX_M7)
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#include <core_cm7.h>
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#elif defined(CONFIG_CPU_CORTEX_M23)
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#include <core_cm23.h>
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#elif defined(CONFIG_CPU_CORTEX_M33)
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#include <core_cm33.h>
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#else
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#error "Unknown Cortex-M device"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_CMSIS_H_ */
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