f1f63dda17
This adds FPU sharing support with a lazy context switching algorithm. Every thread is allowed to use FPU/SIMD registers. In fact, the compiler may insert FPU reg accesses in anycontext to optimize even non-FP code unless the -mgeneral-regs-only compiler flag is used, but Zephyr currently doesn't support such a build. It is therefore possible to do FP access in IRS as well with this patch although IRQs are then disabled to prevent nested IRQs in such cases. Because the thread object grows in size, some tests have to be adjusted. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_THREAD_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM64_THREAD_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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struct _callee_saved {
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uint64_t x19;
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uint64_t x20;
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uint64_t x21;
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uint64_t x22;
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uint64_t x23;
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uint64_t x24;
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uint64_t x25;
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uint64_t x26;
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uint64_t x27;
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uint64_t x28;
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uint64_t x29;
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uint64_t sp_el0;
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uint64_t sp_elx;
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};
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typedef struct _callee_saved _callee_saved_t;
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struct z_arm64_fp_context {
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__int128 q0, q1, q2, q3, q4, q5, q6, q7;
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__int128 q8, q9, q10, q11, q12, q13, q14, q15;
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__int128 q16, q17, q18, q19, q20, q21, q22, q23;
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__int128 q24, q25, q26, q27, q28, q29, q30, q31;
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uint32_t fpsr, fpcr;
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};
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struct _thread_arch {
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#ifdef CONFIG_USERSPACE
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struct arm_mmu_ptables *ptables;
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#endif
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#ifdef CONFIG_FPU_SHARING
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struct z_arm64_fp_context saved_fp_context;
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#endif
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uint8_t exception_depth;
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_THREAD_H_ */
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