d400b8135c
This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
23 lines
1.0 KiB
YAML
23 lines
1.0 KiB
YAML
common:
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tags: linker
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tests:
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tests.application_development.code_relocation:
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filter: not CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
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arch_allow: arm
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extra_configs:
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- CONFIG_RELOCATE_TO_ITCM=y
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tests.application_development.code_relocation_kinetis:
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filter: CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
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arch_allow: arm
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extra_configs:
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- CONFIG_RELOCATE_TO_ITCM=y
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- CONFIG_MPU_ALLOW_FLASH_WRITE=y
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tests.application_development.code_relocation.no_itcm:
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filter: not CONFIG_CPU_HAS_NXP_MPU and not dt_chosen_enabled("zephyr,itcm")
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arch_allow: arm
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extra_sections: _SRAM2_RODATA_SECTION_NAME _SRAM_TEXT_SECTION_NAME _SRAM_RODATA_SECTION_NAME _SRAM_DATA_SECTION_NAME _CUSTOM_SECTION_NAME2
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platform_allow: qemu_cortex_m3 mps2_an385 sam_e70_xplained
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tests.application_development.code_relocation.riscv:
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extra_args: CONF_FILE="prj_riscv.conf"
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platform_allow: qemu_riscv32 qemu_riscv64
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