Daniel Leung 22de29e768 soc: intel_adsp/ace: put syscall helpers in vector code section ... This puts the syscall helpers into the vector code section, and is a tiny TLB optimization. Before this, worst case scenario is that there would 2 instruction TLB misses when both the syscall helpers and the vector code pages are not in TLB cache. With this change, there would be at most 1 instruction TLB miss as now the syscall helper and the vector code (which includes exception handling code and xtensa_do_syscall()) are now in the same page, and the same TLB entry. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2024-11-26 00:12:18 +01:00
..
alder_lake
apollo_lake	drivers/timer/apic_tsc: use ICR as a fallback timeout event source	2024-05-29 08:40:43 +02:00
atom
common
elkhart_lake
intel_adsp	soc: intel_adsp/ace: put syscall helpers in vector code section	2024-11-26 00:12:18 +01:00
intel_ish	soc: intel_ish: remove duplicate hook	2024-09-21 11:29:06 +02:00
intel_niosv	arch: riscv: imply XIP config pushed to SoC level	2024-08-31 06:47:52 -04:00
intel_socfpga	soc: Remove re-defining some defined types	2024-11-18 07:41:23 -05:00
intel_socfpga_std	soc: Remove re-defining some defined types	2024-11-18 07:41:23 -05:00
lakemont
raptor_lake