So far the I2C channel connected to the battery has chosen the option
of Standard-mode 100KHz, but according to the SI(Signal Integrity)
test report, the I2C channel doesn’t meet the tHD;DAT Margin/Threshold
in the SI test. In fact, the timing could be adjusted by changing the
settings in the related timing registers in EC, but unfortunately the
limitation exists due to the fact that the timing registers have been
currently occupied by another channel for the same reason, that is,
adjusting the timing.
However, according to the I2C specification, the Standard-mode (Sm)
has a bit rate up to 100 kbit/s, so far the battery use the option
of standard mode 100KHz in the SMCLK setting register. This SMCLK
setting register also provides standard mode 50KHz for usage.
According to another SI test reports, so far the Standard-mode 50KHz
setting looks good in the SI test.
Therefore, add a #define I2C_SPEED_DT allows the device tree to
write a specified speed without causing i2c_configure() and
i2c_get_config() to return error.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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