58e24f37fb
The ARM Cortex-M 321 application note is stressing that when enabling interrupts by executing CPSIE i(f), or by MSR instructions (on PRIMASK, FAULTMASK, or BASEPRI registers), there is a need for synchronization barrier instructions, if there is a requirement for the effect of enabling interrupts to be recongnized immediately. _arch_irq_unlock() is invoked in several places, therefore, we add the barriers to make the interrupt enabling function applicable to all usage scenarios. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no> |
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| .. | ||
| cortex_m | ||
| arch.h | ||
| syscall.h | ||