Stephanos Ioannidis dc3c9f3560 arch: riscv: Introduce code model options ... This commit introduces a new Kconfig choice for configuring the code model used for compilation. All three code models specified by the RISC-V ELF psABI specification are supported: medlow, medany and large. For RV32, the `medlow` code model is always selected. For RV64, the `large` code model is selected if the SRAM or kernel VM base address is greater than or equal to 4 GiB; otherwise, the `medany` code model is selected. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>		2025-07-19 15:43:09 -04:00
..
arc	arch: arc: support CONFIG_ROM_START_OFFSET	2025-07-19 15:32:03 -04:00
arm	arch: arm: cortex_m: Modifed FPU save and restore helpers	2025-07-19 13:45:07 -04:00
arm64	arch: arm64: core: fpu: mark unused function argument	2025-07-11 08:18:43 -10:00
common	arch: arc: support CONFIG_ROM_START_OFFSET	2025-07-19 15:32:03 -04:00
mips
posix	arch/posix: Remove support for CONFIG_NATIVE_APPLICATION	2025-07-19 09:38:15 +02:00
riscv	arch: riscv: Introduce code model options	2025-07-19 15:43:09 -04:00
rx	include: arch: rx: Change data symbol name	2025-06-26 14:07:03 +02:00
sparc
x86
xtensa	xtensa: tracing: instrument thread switching	2025-07-08 18:34:11 -05:00
archs.yml
CMakeLists.txt
Kconfig	riscv: select ATOMIC_OPERATIONS based on RISCV_ISA_EXT_A	2025-06-30 15:17:47 -05:00