Some hardware has "interesting" configuration like asymmetric default
interrupt masking (the intel_adsp devices in particular, but x86's
IO-APIC driver has tripped over this in the past too) that needs
special treatment if you want to run something on "core 1"
specifically, and 1cpu test cases pretty much by definition are going
to have been written without SMP details in mind. Switch the logic
around a tiny bit such that these test cases always run on CPU ID zero
explicitly.
Actually in practice this was ALMOST guaranteed to be true already,
because test setup and happens serially, having been started on the
main thread, which starts on CPU 0 by definition. Then the test
teardown aborts all the spawned threads that might have been running
on CPUs 1+, so those reach idle, and the next test case starts
syncronously on the same thread (and thus CPU) where it started. But
nonetheless that wasn't actually enforced, and we've found at least
one simulation environment where timing conspires to break things.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
adc901aa6a