Erwan Gouriou 6cbb3f5eec drivers: clock_control: stm32: Fixed domain clock configuration ... In some case, we may need to describe a domain clock for a device while there is no way to configure it (ex: USB clock set on PLL_Q output on F405 devices > It is not selectable). Then, configuring a device clock domain in the clock_control driver will allow to retrieve its subsys rate. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>		2023-01-12 12:46:53 +01:00
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zephyr	drivers: clock_control: stm32: Fixed domain clock configuration	2023-01-12 12:46:53 +01:00