Gerson Fernando Budke f93ee9508b soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support ... PSoC-6 SoC needs that user define the nvic interrupt number to bind with the peripheral interrupt line for the Cortex-M0+ CPU. It uses a multiplex before any NVIC interrupt line. The interrupt vector is selected using interrupt-parent property with the intmux_chN number reference. Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt. A tipical use is GPIO interrupt handle and user is responsable to define interrupt line, priority and take care of enable same peripheral instance on both CPUs only when appropriated. Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>		2021-01-20 17:54:09 -06:00
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arc	cache: Rename CACHE_FLUSHING to CACHE_MANAGEMENT	2021-01-19 14:31:02 -05:00
arm	soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support	2021-01-20 17:54:09 -06:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	soc/riscv: add the QEMU "RISC-V VirtIO board"	2021-01-15 13:06:33 -05:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	drivers: i2c_dw: Remove hard-coded instance count assumption	2021-01-19 14:52:29 -05:00
xtensa	xtensa: fix an assembly warning in start_address.S	2021-01-14 11:41:39 -05:00
Kconfig	timing: introduce timing functions as a generic feature	2020-09-05 13:28:38 -05:00