zephyr/dts/xtensa
Flavio Ceolin 301055dec0 intel-adsp/ace: pm: Only core 0 can d0i3
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.

Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-05-24 09:53:04 -05:00
..
espressif drivers: esp32: SDHC implementation 2024-04-30 18:23:06 +02:00
intel intel-adsp/ace: pm: Only core 0 can d0i3 2024-05-24 09:53:04 -05:00
nxp nxp: imx8ulp: add audio-related nodes 2024-04-23 15:36:01 +02:00
dc233c.dtsi xtensa: dc233c: Fix build warning in DTS on leading zeros 2024-04-03 20:41:45 -04:00
sample_controller.dtsi
xtensa.dtsi