dbd0ac40ce
Add indirect CSR access to access CLIC register to satisfy the current CLIC spec (Version v0.9, 2024-06-28: Draf). Add CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS for legacy CLIC implementation with memory-mapped CLIC register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
77 lines
2.2 KiB
Plaintext
77 lines
2.2 KiB
Plaintext
# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config CLIC
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bool "RISC-V Core Local Interrupt Controller (CLIC)"
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default y
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depends on DT_HAS_NUCLEI_ECLIC_ENABLED || DT_HAS_RISCV_CLIC_ENABLED
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select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
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help
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Core Local Interrupt Controller provide low-latency, vectored,
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preemptive interrupts for RISC-V systems.
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config NUCLEI_ECLIC
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bool "Enhanced Core Local Interrupt Controller (ECLIC)"
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default y
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depends on DT_HAS_NUCLEI_ECLIC_ENABLED
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select CLIC
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select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
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select CLIC_SMCLICCONFIG_EXT
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select LEGACY_CLIC_MEMORYMAP_ACCESS
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help
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Interrupt controller for Nuclei SoC core.
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config NRFX_CLIC
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bool "VPR Core Local Interrpt Controller (CLIC)"
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default y
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depends on DT_HAS_NORDIC_NRF_CLIC_ENABLED
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select GEN_IRQ_VECTOR_TABLE
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help
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Interrupt controller for Nordic VPR cores.
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if CLIC
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config CLIC_SMCLICSHV_EXT
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bool
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help
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The selective hardware vectoring extension gives users the flexibility
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to select the behavior for each interrupt. The CLIC driver needs to
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implement the riscv_clic_irq_vector_set() function.
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config CLIC_SMCLICCONFIG_EXT
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bool
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help
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Enables the SMCLICCONFIG extension, allowing configuration of CLIC
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parameters such as the number of interrupt level bits.
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config CLIC_PARAMETER_INTCTLBITS
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int "The number of modifiable bits in the clicintctl registers"
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range 0 8
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default 8
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help
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This option specifies the number of modifiable bits in the clicintctl
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registers.
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config CLIC_PARAMETER_MNLBITS
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int "The number of bits in CLICINTCTLBITS to encode the interrupt level"
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range 0 CLIC_PARAMETER_INTCTLBITS
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default 0
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help
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This option specifies the number of bits in CLICINTCTLBITS assigned to
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encode the interrupt level at machine mode.
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config LEGACY_CLIC_MEMORYMAP_ACCESS
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bool
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help
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Enables legacy CLIC, allowing access to CLIC registers through
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memory-mapped access instead of indirect CSR access.
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config LEGACY_CLIC
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bool "Use the legacy clic specification"
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depends on RISCV_HAS_CLIC
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help
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Enables legacy clic, where smclicshv extension is not supported and
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hardware vectoring is set via mode bits of mtvec.
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endif # CLIC
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