65fb61bc68
Implement `riscv_plic_irq_set_pending()` to trigger a software-generated interrupt. The "4. Interrupt Pending Bits" of the riscv-plic specs described the reading of the pending bits, but not the writing Since not all PLIC implementations support software-generated interrupt, the function is compiled only when `CONFIG_PLIC_SUPPORTS_SOFT_INTERRUPT` is enabled on PLIC that supports it, such as the Andes' NCEPLIC100. Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com> |
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