Carlo Caione 5fece03d7d riscv: Introduce Zicsr and Zifencei extensions ... And enable the new extensions on all the SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2022-08-29 16:57:18 +02:00
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arc	ARC: boards: QEMU: hs6x: minor description polish	2022-08-22 10:23:14 +00:00
arm	soc: arm/riscv: gigadevice: enable reset controller by default	2022-08-29 10:30:49 +02:00
arm64	soc/arm64: Do not allow userspace to directly access peripherals	2022-08-05 06:28:57 +01:00
mips	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nios2	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
posix	cmake: Update CONFIG_ASAN support	2022-08-19 08:30:01 +02:00
riscv	riscv: Introduce Zicsr and Zifencei extensions	2022-08-29 16:57:18 +02:00
sparc	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
x86	i2c: Remove unncessary HAS_I2C_DW Kconfig symbol	2022-08-01 18:01:44 +02:00
xtensa	logging: Intel ADSP mtrace logging backend	2022-08-29 10:43:42 +02:00
Kconfig	kconfig: soc and shield cleanup	2021-06-11 16:13:22 +02:00