Lauren Murphy c1711997bc debug: coredump: add xtensa coredump ... Adds Xtensa as supported architecture for coredump. Fixes a few typos in documentation, Kconfig and a C file. Dumps minimal set of registers shown by 'info registers' in GDB for the sample_controller and ESP32 SOCs. Updates tests. Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>		2021-12-14 07:40:55 -05:00
..
arc	soc: arc: fix ARC_HAS_ACCL_REGS settings	2021-12-02 11:32:14 -06:00
arm	arch: cortex_m: Fix dwt cyccnt assert	2021-12-10 12:27:49 +01:00
arm64	xenvm: arm64: add Xen Enlighten and event channel support	2021-12-07 12:15:38 -05:00
common	cmake: CMake linker script generator pass handling	2021-11-08 20:45:07 +01:00
nios2	arch: nios2: Fix 10.4 violations	2021-04-10 09:59:37 -04:00
posix	pm: Remove unused parameter	2021-11-17 11:15:49 -05:00
riscv	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00
sparc	arch/sparc: Add hook for CONFIG_SCHED_THREAD_USAGE accounting in ISRs	2021-11-08 21:32:20 -05:00
x86	x86: acpi: Fix address-of-packed-mem warning	2021-12-10 14:08:59 +01:00
xtensa	debug: coredump: add xtensa coredump	2021-12-14 07:40:55 -05:00
CMakeLists.txt
Kconfig	coredump: add support for RISC-V	2021-12-08 08:54:32 -05:00