66cae83ff7
Origin: Microchip CPG Purpose: Peripheral firmware library for MEC1501 Version: 0.1 License: Apache Maintained-by: External Signed-off-by: Scott Worley <scott.worley@microchip.com>
289 lines
6.6 KiB
C
289 lines
6.6 KiB
C
/**
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*
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* Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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/** @file cpu.h
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*MEC1701 CPU abstractions
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*/
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/** @defgroup cpu
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*/
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#ifndef _CPU_H
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#define _CPU_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __CC_ARM /* Keil ARM MDK */
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#ifndef UINT8_C
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#define UINT8_C(x) (unsigned char)(x)
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#endif
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#ifndef UINT16_C
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#define UINT16_C(x) (unsigned int)(x)
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#endif
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#ifndef UINT32_C
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#define UINT32_C(x) (unsigned long)(x)
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#endif
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#define USED __attribute__((used))
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#define WEAK __attribute__((weak))
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#define INLINE __inline
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#define NORETURN __declspec(noreturn)
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#define PACKED __packed
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#define CPU_GET_INTERRUPT_STATE() __get_PRIMASK()
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#define CPU_SET_INTERRUPT_STATE(x) __set_PRIMASK((x))
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/*
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* Keil MDK intrisic __disable_irq() returns the value of MSR PRIMASK
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* before disabling interrupts.
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*/
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#define CPU_DISABLE_INTERRUPTS() __disable_irq()
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#define CPU_GET_DISABLE_INTERRUPTS(x) {(x) = __disable_irq();}
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#define CPU_RESTORE_INTERRUPTS(x) { if (!(x)) { __enable_irq(); } }
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#define CPU_ENABLE_INTERRUPTS() __enable_irq()
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#define CPU_NOP() __nop()
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#define CPU_WAIT_FOR_INTR() __wfi()
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#define CPU_REV(x) __rev(x)
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#define CPU_CLZ(x) __clz(x)
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/*
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* The microsecond delay register is implemented in a Normal Data Memory
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* Region. Normal regions have relaxed data ordering semantics. This can
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* cause issues because writes to this register can complete before a
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* previous write to Device or Strongly ordered memory. Please use the
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* inline code after this definition. It uses the Data Synchronization
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* Barrier instruction to insure all outstanding writes complete before
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* the instruction after DSB is executed.
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* #define MEC2016_DELAY_REG *((volatile uint8_t*) MEC2016_DELAY_REG_BASE)
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*/
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static inline void MICROSEC_DELAY(unsigned char n)
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{
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volatile unsigned long *pdly_reg;
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pdly_reg = (volatile unsigned long *)0x10000000ul;
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__asm volatile (
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"\tstrb n, [pdly_reg]\n"
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"\tldrb n, [pdly_reg]\n"
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"\tadd n, #0\n"
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"\tdmb\n"
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);
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}
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#elif defined(__XC32_PART_SUPPORT_VERSION) /* Microchip XC32 compiler customized GCC */
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#error "!!! FORCED BUILD ERROR: compiler.h XC32 support has not been implemented !!!"
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#elif defined(__GNUC__) && defined(__ARM_EABI__) /* GCC for ARM (arm-none-eabi-gcc) */
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#include <stdint.h>
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#include <stddef.h>
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#ifndef __always_inline
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#define __always_inline inline __attribute__((always_inline))
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#endif
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static __always_inline void __NOP_THUMB2(void)
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{
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__asm volatile ("nop");
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}
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#define CPU_NOP() __NOP_THUMB2()
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static __always_inline void __WFI_THUMB2(void)
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{
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__asm volatile ("dsb");
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__asm volatile ("isb");
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__asm volatile ("wfi");
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__asm volatile ("nop");
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__asm volatile ("nop");
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__asm volatile ("nop");
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}
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#define CPU_WAIT_FOR_INTR() __WFI_THUMB2()
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/* We require user have ARM CMSIS header files available and configured
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* core_cmFunc.h includes inlines for global interrupt control.
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* For some reason, CMSIS __disable_irq for GCC does not return current PRIMASK
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* value. */
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static __always_inline uint32_t __get_disable_irq(void)
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{
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uint32_t pri_mask;
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__asm volatile (
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"\tmrs %0, primask\n"
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"\tcpsid i\n"
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"\tdsb\n"
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"\tisb\n"
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: "=r" (pri_mask) :: "memory"
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);
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return pri_mask;
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}
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static __always_inline uint32_t __get_primask(void)
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{
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uint32_t pri_mask;
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__asm volatile (
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"\tmrs %0, primask\n"
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"\tisb\n"
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: "=r" (pri_mask) :: "memory"
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);
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return pri_mask;
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}
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static __always_inline void __enable_irqs(void)
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{
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__asm volatile ("cpsie i" : : : "memory");
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}
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static __always_inline void __disable_irqs(void)
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{
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__asm volatile (
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"\tcpsid i\n"
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"\tdsb\n"
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"\tisb\n" : : : "memory");
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}
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#define CPU_GET_INTERRUPT_STATE() __get_primask()
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#define CPU_GET_DISABLE_INTERRUPTS(x) {(x) = __get_disable_irq();}
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#define CPU_RESTORE_INTERRUPTS(x) { if (!(x)) { __enable_irqs(); } }
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#define CPU_ENABLE_INTERRUPTS() __enable_irqs()
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#define CPU_DISABLE_INTERRUPTS() __disable_irqs()
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static __always_inline uint32_t __REV_THUMB2(uint32_t u32)
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{
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return __builtin_bswap32(u32);
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}
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#define CPU_REV(x) __REV_THUMB2(x)
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/*
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* __builtin_clz() will not be available if user compiles with built-ins disabled flag.
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*/
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#define CPU_CLZ(x) __builtin_clz(x)
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static inline __attribute__((always_inline, noreturn)) void CPU_JMP(uint32_t addr)
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{
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addr |= (1ul << 0);
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__asm volatile (
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"\n\t"
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"\tBX %0 \n"
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"\tNOP \n"
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: /* no outputs */
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:"r"(addr)
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:);
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while(1);
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}
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/*
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* The microsecond delay register is implemented in a Normal Data Memory
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* Region. Normal regions have relaxed data ordering semantics. This can
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* cause issues because writes to this register can complete before a
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* previous write to Device or Strongly ordered memory. Please use the
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* inline code after this definition. It uses the Data Synchronization
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* Barrier instruction to insure all outstanding writes complete before
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* the instruction after DSB is executed.
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* #define MEC2016_DELAY_REG *((volatile uint8_t*) MEC2016_DELAY_REG_BASE)
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*/
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static __always_inline void MICROSEC_DELAY(uint8_t n)
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{
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uint32_t dly_reg_addr = 0x10000000ul;
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__asm volatile (
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"\tstrb %0, [%1]\n"
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"\tldrb %0, [%1]\n"
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"\tadd %0, #0\n"
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"\tdmb\n"
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:
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: "r" (n), "r" (dly_reg_addr)
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: "memory"
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);
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}
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static __always_inline void write_read_back8(volatile uint8_t* addr, uint8_t val)
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{
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__asm__ __volatile__ (
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"\n\t"
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"strb %1, [%0] \n\t"
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"ldrb %1, [%0] \n\t"
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: /* No outputs */
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: "r" (addr), "r" (val)
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: "memory"
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);
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}
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static __always_inline void write_read_back16(volatile uint16_t* addr, uint16_t val)
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{
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__asm__ __volatile__ (
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"\n\t"
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"strh %1, [%0] \n\t"
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"ldrh %1, [%0] \n\t"
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: /* No outputs */
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: "r" (addr), "r" (val)
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: "memory"
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);
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}
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static __always_inline void write_read_back32(volatile uint32_t* addr, uint32_t val)
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{
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__asm__ __volatile__ (
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"\n\t"
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"str %1, [%0] \n\t"
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"ldr %1, [%0] \n\t"
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: /* No outputs */
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: "r" (addr), "r" (val)
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: "memory"
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);
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}
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#else /* Unknown compiler */
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#error "!!! FORCED BUILD ERROR: cpu.h Unknown compiler !!!"
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#endif
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#endif /* #ifndef _CPU_H */
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/** @}
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*/
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