Mateusz Holenko ebd349091a dts: riscv32: fix reg-names for liteeth ... Liteeth exposes two memory regions: * set of rx/tx buffers (aka slots) to exchange packets, * control and status registers. Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>		2019-07-23 10:51:21 +02:00
..
microsemi-miv.dtsi	dts: riscv32: microsemi-miv: add flash and sram	2019-05-10 10:34:31 -05:00
riscv32-fe310.dtsi	dts: cleanup missing #{address,size}-cells	2019-06-20 22:48:57 -05:00
riscv32-litex-vexriscv.dtsi	dts: riscv32: fix reg-names for liteeth	2019-07-23 10:51:21 +02:00
rv32m1_ri5cy.dtsi	dts: riscv32: rv32m1: Disable unused interrupt multiplexers	2019-07-20 17:23:20 -04:00
rv32m1_zero_riscy.dtsi	dts: riscv32: rv32m1: Disable unused interrupt multiplexers	2019-07-20 17:23:20 -04:00
rv32m1.dtsi	dts: riscv32: rv32m1: Disable unused interrupt multiplexers	2019-07-20 17:23:20 -04:00