0325a3d972
The MVIC is no longer supported, and only the APIC-based interrupt subsystem remains. Thus this layer of indirection is unnecessary. This also corrects an oversight left over from the Jailhouse x2APIC implementation affecting EOI delivery for direct ISRs only. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
413 lines
11 KiB
C
413 lines
11 KiB
C
/*
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* Copyright (c) 1984-2008, 2011-2015 Wind River Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* driver for x86 CPU local APIC (as an interrupt controller)
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*/
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#include <kernel.h>
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#include <kernel_structs.h>
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#include <arch/cpu.h>
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#include <zephyr/types.h>
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#include <string.h>
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#include <sys/__assert.h>
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#include <arch/x86/msr.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <drivers/interrupt_controller/loapic.h> /* public API declarations */
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#include <init.h>
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#include <drivers/interrupt_controller/sysapic.h>
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/* Local APIC Version Register Bits */
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#define LOAPIC_VERSION_MASK 0x000000ff /* LO APIC Version mask */
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#define LOAPIC_MAXLVT_MASK 0x00ff0000 /* LO APIC Max LVT mask */
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#define LOAPIC_PENTIUM4 0x00000014 /* LO APIC in Pentium4 */
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#define LOAPIC_LVT_PENTIUM4 5 /* LO APIC LVT - Pentium4 */
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#define LOAPIC_LVT_P6 4 /* LO APIC LVT - P6 */
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#define LOAPIC_LVT_P5 3 /* LO APIC LVT - P5 */
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/* Local APIC Vector Table Bits */
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#define LOAPIC_VECTOR 0x000000ff /* vectorNo */
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#define LOAPIC_MODE 0x00000700 /* delivery mode */
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#define LOAPIC_FIXED 0x00000000 /* delivery mode: FIXED */
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#define LOAPIC_SMI 0x00000200 /* delivery mode: SMI */
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#define LOAPIC_NMI 0x00000400 /* delivery mode: NMI */
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#define LOAPIC_EXT 0x00000700 /* delivery mode: ExtINT */
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#define LOAPIC_IDLE 0x00000000 /* delivery status: Idle */
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#define LOAPIC_PEND 0x00001000 /* delivery status: Pend */
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#define LOAPIC_HIGH 0x00000000 /* polarity: High */
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#define LOAPIC_LOW 0x00002000 /* polarity: Low */
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#define LOAPIC_REMOTE 0x00004000 /* remote IRR */
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#define LOAPIC_EDGE 0x00000000 /* trigger mode: Edge */
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#define LOAPIC_LEVEL 0x00008000 /* trigger mode: Level */
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/* Local APIC Spurious-Interrupt Register Bits */
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#define LOAPIC_ENABLE 0x100 /* APIC Enabled */
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#define LOAPIC_FOCUS_DISABLE 0x200 /* Focus Processor Checking */
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#if CONFIG_LOAPIC_SPURIOUS_VECTOR_ID == -1
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#define LOAPIC_SPURIOUS_VECTOR_ID (CONFIG_IDT_NUM_VECTORS - 1)
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#else
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#define LOAPIC_SPURIOUS_VECTOR_ID CONFIG_LOAPIC_SPURIOUS_VECTOR_ID
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#endif
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#define LOPIC_SSPND_BITS_PER_IRQ 1 /* Just the one for enable disable*/
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#define LOPIC_SUSPEND_BITS_REQD (ROUND_UP((LOAPIC_IRQ_COUNT * LOPIC_SSPND_BITS_PER_IRQ), 32))
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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#include <power/power.h>
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u32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
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static u32_t loapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
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#endif
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/*
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* this should not be a function at all, really, it should be
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* hand-coded in include/drivers/sysapic.h. but for now it remains
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* a function, just moved here from drivers/timer/loapic_timer.c
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* where it REALLY didn't belong.
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*/
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#ifdef CONFIG_X2APIC
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void z_x2apic_eoi(void)
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{
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x86_write_x2apic(LOAPIC_EOI, 0);
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}
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#endif
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/**
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*
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* @brief Initialize the Local APIC or xAPIC
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*
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* This routine initializes Local APIC or xAPIC.
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*
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* @return N/A
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*
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*/
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static int loapic_init(struct device *unused)
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{
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ARG_UNUSED(unused);
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s32_t loApicMaxLvt; /* local APIC Max LVT */
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/*
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* enable the local APIC. note that we use xAPIC mode here, since
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* x2APIC access is not enabled until the next step (if at all).
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*/
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x86_write_xapic(LOAPIC_SVR,
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x86_read_xapic(LOAPIC_SVR) | LOAPIC_ENABLE);
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#ifdef CONFIG_X2APIC
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/*
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* turn on x2APIC mode. we trust the config option, so
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* we don't check CPUID to see if x2APIC is supported.
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*/
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u64_t msr = z_x86_msr_read(X86_APIC_BASE_MSR);
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msr |= X86_APIC_BASE_MSR_X2APIC;
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z_x86_msr_write(X86_APIC_BASE_MSR, msr);
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#endif
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loApicMaxLvt = (x86_read_loapic(LOAPIC_VER) & LOAPIC_MAXLVT_MASK) >> 16;
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/* reset the DFR, TPR, TIMER_CONFIG, and TIMER_ICR */
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#ifndef CONFIG_X2APIC
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x86_write_loapic(LOAPIC_DFR, 0xffffffff); /* no DFR in x2APIC mode */
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#endif
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x86_write_loapic(LOAPIC_TPR, 0x0);
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x86_write_loapic(LOAPIC_TIMER_CONFIG, 0x0);
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x86_write_loapic(LOAPIC_TIMER_ICR, 0x0);
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/* program Local Vector Table for the Virtual Wire Mode */
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/* skip LINT0/LINT1 for Jailhouse guest case, because we won't
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* ever be waiting for interrupts on those
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*/
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/* set LINT0: extInt, high-polarity, edge-trigger, not-masked */
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x86_write_loapic(LOAPIC_LINT0, (x86_read_loapic(LOAPIC_LINT0) &
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~(LOAPIC_MODE | LOAPIC_LOW |
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LOAPIC_LEVEL | LOAPIC_LVT_MASKED)) |
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(LOAPIC_EXT | LOAPIC_HIGH | LOAPIC_EDGE));
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/* set LINT1: NMI, high-polarity, edge-trigger, not-masked */
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x86_write_loapic(LOAPIC_LINT1, (x86_read_loapic(LOAPIC_LINT1) &
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~(LOAPIC_MODE | LOAPIC_LOW |
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LOAPIC_LEVEL | LOAPIC_LVT_MASKED)) |
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(LOAPIC_NMI | LOAPIC_HIGH | LOAPIC_EDGE));
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/* lock the Local APIC interrupts */
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x86_write_loapic(LOAPIC_TIMER, LOAPIC_LVT_MASKED);
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x86_write_loapic(LOAPIC_ERROR, LOAPIC_LVT_MASKED);
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if (loApicMaxLvt >= LOAPIC_LVT_P6) {
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x86_write_loapic(LOAPIC_PMC, LOAPIC_LVT_MASKED);
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}
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if (loApicMaxLvt >= LOAPIC_LVT_PENTIUM4) {
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x86_write_loapic(LOAPIC_THERMAL, LOAPIC_LVT_MASKED);
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}
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#if CONFIG_LOAPIC_SPURIOUS_VECTOR
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x86_write_loapic(LOAPIC_SVR, (x86_read_loapic(LOAPIC_SVR) & 0xFFFFFF00) |
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(LOAPIC_SPURIOUS_VECTOR_ID & 0xFF));
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#endif
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/* discard a pending interrupt if any */
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#if CONFIG_EOI_FORWARDING_BUG
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z_lakemont_eoi();
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#else
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x86_write_loapic(LOAPIC_EOI, 0);
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#endif
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return 0;
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}
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/**
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*
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* @brief Set the vector field in the specified RTE
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*
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* This associates an IRQ with the desired vector in the IDT.
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*
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* @return N/A
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*/
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void z_loapic_int_vec_set(unsigned int irq, /* IRQ number of the interrupt */
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unsigned int vector /* vector to copy into the LVT */
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)
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{
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unsigned int oldLevel; /* previous interrupt lock level */
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/*
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* The following mappings are used:
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*
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* IRQ0 -> LOAPIC_TIMER
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* IRQ1 -> LOAPIC_THERMAL
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* IRQ2 -> LOAPIC_PMC
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* IRQ3 -> LOAPIC_LINT0
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* IRQ4 -> LOAPIC_LINT1
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* IRQ5 -> LOAPIC_ERROR
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*
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* It's assumed that LVTs are spaced by 0x10 bytes
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*/
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/* update the 'vector' bits in the LVT */
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oldLevel = irq_lock();
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x86_write_loapic(LOAPIC_TIMER + (irq * 0x10),
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(x86_read_loapic(LOAPIC_TIMER + (irq * 0x10)) &
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~LOAPIC_VECTOR) | vector);
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irq_unlock(oldLevel);
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}
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/**
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*
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* @brief Enable an individual LOAPIC interrupt (IRQ)
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*
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* @param irq the IRQ number of the interrupt
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*
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* This routine clears the interrupt mask bit in the LVT for the specified IRQ
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*
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* @return N/A
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*/
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void z_loapic_irq_enable(unsigned int irq)
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{
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unsigned int oldLevel; /* previous interrupt lock level */
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/*
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* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
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* and ths assumption concerning LVT spacing.
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*/
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/* clear the mask bit in the LVT */
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oldLevel = irq_lock();
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x86_write_loapic(LOAPIC_TIMER + (irq * 0x10),
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x86_read_loapic(LOAPIC_TIMER + (irq * 0x10)) &
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~LOAPIC_LVT_MASKED);
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irq_unlock(oldLevel);
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}
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/**
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*
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* @brief Disable an individual LOAPIC interrupt (IRQ)
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*
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* @param irq the IRQ number of the interrupt
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*
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* This routine clears the interrupt mask bit in the LVT for the specified IRQ
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*
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* @return N/A
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*/
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void z_loapic_irq_disable(unsigned int irq)
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{
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unsigned int oldLevel; /* previous interrupt lock level */
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/*
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* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
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* and ths assumption concerning LVT spacing.
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*/
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/* set the mask bit in the LVT */
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oldLevel = irq_lock();
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x86_write_loapic(LOAPIC_TIMER + (irq * 0x10),
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x86_read_loapic(LOAPIC_TIMER + (irq * 0x10)) |
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LOAPIC_LVT_MASKED);
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irq_unlock(oldLevel);
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}
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/**
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* @brief Find the currently executing interrupt vector, if any
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*
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* This routine finds the vector of the interrupt that is being processed.
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* The ISR (In-Service Register) register contain the vectors of the interrupts
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* in service. And the higher vector is the identification of the interrupt
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* being currently processed.
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*
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* This function must be called with interrupts locked in interrupt context.
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*
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* ISR registers' offsets:
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* --------------------
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* | Offset | bits |
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* --------------------
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* | 0100H | 0:31 |
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* | 0110H | 32:63 |
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* | 0120H | 64:95 |
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* | 0130H | 96:127 |
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* | 0140H | 128:159 |
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* | 0150H | 160:191 |
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* | 0160H | 192:223 |
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* | 0170H | 224:255 |
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* --------------------
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*
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* @return The vector of the interrupt that is currently being processed, or -1
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* if no IRQ is being serviced.
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*/
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int z_irq_controller_isr_vector_get(void)
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{
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int pReg, block;
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/* Block 0 bits never lit up as these are all exception or reserved
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* vectors
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*/
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for (block = 7; likely(block > 0); block--) {
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pReg = x86_read_loapic(LOAPIC_ISR + (block * 0x10));
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if (pReg) {
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return (block * 32) + (find_msb_set(pReg) - 1);
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}
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}
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return -1;
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}
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static int loapic_suspend(struct device *port)
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{
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volatile u32_t lvt; /* local vector table entry value */
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int loapic_irq;
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ARG_UNUSED(port);
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(void)memset(loapic_suspend_buf, 0, (LOPIC_SUSPEND_BITS_REQD >> 3));
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for (loapic_irq = 0; loapic_irq < LOAPIC_IRQ_COUNT; loapic_irq++) {
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if (_irq_to_interrupt_vector[LOAPIC_IRQ_BASE + loapic_irq]) {
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/* Since vector numbers are already present in RAM/ROM,
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* We save only the mask bits here.
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*/
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lvt = x86_read_loapic(LOAPIC_TIMER + (loapic_irq * 0x10));
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if ((lvt & LOAPIC_LVT_MASKED) == 0U) {
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sys_bitfield_set_bit((mem_addr_t)loapic_suspend_buf,
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loapic_irq);
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}
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}
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}
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loapic_device_power_state = DEVICE_PM_SUSPEND_STATE;
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return 0;
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}
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int loapic_resume(struct device *port)
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{
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int loapic_irq;
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ARG_UNUSED(port);
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/* Assuming all loapic device registers lose their state, the call to
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* z_loapic_init(), should bring all the registers to a sane state.
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*/
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loapic_init(NULL);
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for (loapic_irq = 0; loapic_irq < LOAPIC_IRQ_COUNT; loapic_irq++) {
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if (_irq_to_interrupt_vector[LOAPIC_IRQ_BASE + loapic_irq]) {
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/* Configure vector and enable the required ones*/
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z_loapic_int_vec_set(loapic_irq,
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_irq_to_interrupt_vector[LOAPIC_IRQ_BASE + loapic_irq]);
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if (sys_bitfield_test_bit((mem_addr_t) loapic_suspend_buf,
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loapic_irq)) {
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z_loapic_irq_enable(loapic_irq);
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}
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}
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}
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loapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
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return 0;
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}
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/*
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* Implements the driver control management functionality
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* the *context may include IN data or/and OUT data
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*/
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static int loapic_device_ctrl(struct device *port, u32_t ctrl_command,
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void *context, device_pm_cb cb, void *arg)
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{
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int ret = 0;
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
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ret = loapic_suspend(port);
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} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
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ret = loapic_resume(port);
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}
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} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
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*((u32_t *)context) = loapic_device_power_state;
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}
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if (cb) {
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cb(port, ret, context, arg);
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}
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return ret;
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}
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SYS_DEVICE_DEFINE("loapic", loapic_init, loapic_device_ctrl, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#else
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SYS_INIT(loapic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
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#if CONFIG_LOAPIC_SPURIOUS_VECTOR
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extern void z_loapic_spurious_handler(void);
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NANO_CPU_INT_REGISTER(z_loapic_spurious_handler, NANO_SOFT_IRQ,
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LOAPIC_SPURIOUS_VECTOR_ID >> 4,
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LOAPIC_SPURIOUS_VECTOR_ID, 0);
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#endif
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