Jay Vasanth d0fe965b9f drivers: espi_saf: Add Microchip MEC172x eSPI SAF version 2 driver ... Microchip MEC172x has a modified eSPI SAF hardware implementation. Hardware changes include multiple clock dividers for each SPI flash device and data transfer using QMSPI local DMA. espi reset interrupt is made a higer priority in MEC172x devicetree because espi reset event resets all espi hardware and we don't to want to service any other espi interrupt blocks when espi reset occurs. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>		2022-10-28 14:29:46 -05:00
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arc	smp: Kconfig: Move to using MP_MAX_NUM_CPUS	2022-10-20 22:04:10 +09:00
arm	drivers: espi_saf: Add Microchip MEC172x eSPI SAF version 2 driver	2022-10-28 14:29:46 -05:00
arm64	boards: fvp_baser_aemv8r: remove SOC_FVP_AEMV8R_EL2_INIT code	2022-10-12 18:46:49 +09:00
mips	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nios2	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
posix	cmake: Update CONFIG_ASAN support	2022-08-19 08:30:01 +02:00
riscv	it8xxx2: support relocating ISR code to RAM	2022-10-21 20:31:47 +02:00
sparc	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
x86	soc: raptor_lake: Cleanup CMakeLists	2022-10-25 09:50:15 -05:00
xtensa	soc: xtensa: intel_adsp: Convert CONFIG_MP_NUM_CPUS handling	2022-10-26 12:00:53 +02:00
Kconfig