d5168a8d96
The ESP32 series MCUs allow to set a timeout which triggers an error if the SCL line is unchanged for the specified amount of time. By default, the ESP-IDF HAL sets the timeout to an arbitrary value of 10 times the bus cycle. This is not sufficient for chips like the TI bq76952, which pulls the SCL line low (clock stretching) for several 100 µs. The timeout should also not be dependent on the chosen bitrate, as it is defined by the time a chip needs for internal calculation before it can provide requested data or continue communication. This commit adds a property to devicetree to allow configuration of the scl timeout. This value is set via direct register access, as the ESP-IDF HAL does not provide access to the enable bit and does not give any information about the maximum size of the timeout (defined in I2C clock cycles in the register). Fixes #51351 Signed-off-by: Martin Jäger <martin@libre.solar> |
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| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||