0106e8d14c
Introduce a new arch level Kconfig option to signal the implementation of the RISCV Privileged ISA spec. This replaces SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific property, nor a SoC family. Note that the SoC family naming scheme will be fixed in upcoming commits. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
83 lines
2.5 KiB
YAML
83 lines
2.5 KiB
YAML
common:
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tags:
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- kernel
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- interrupt
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- isr_table
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tests:
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arch.interrupt.gen_isr_table.arm_baseline:
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platform_allow: qemu_cortex_m3
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filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE
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extra_configs:
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- CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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arch.interrupt.gen_isr_table.arm_baseline.linker_generator:
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platform_allow: qemu_cortex_m3
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filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE
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tags:
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- linker_generator
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extra_configs:
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- CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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- CONFIG_CMAKE_LINKER_GENERATOR=y
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arch.interrupt.gen_isr_table.arm_mainline:
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platform_allow: qemu_cortex_m3
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platform_exclude:
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- stmf103_mini
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- nucleo_f103rb
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- olimexino_stm32
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- stm32_min_dev_black
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- stm32_min_dev_blue
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- usb_kw24d512
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- v2m_beetle
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- cc1352r1_launchxl
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- cc26x2r1_launchxl
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- olimex_stm32_h103
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- cc1352r_sensortag
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filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV7_M_ARMV8_M_MAINLINE
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extra_configs:
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- CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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arch.interrupt.gen_isr_table.disabled:
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platform_allow: qemu_cortex_m3
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extra_configs:
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- CONFIG_GEN_ISR_TABLES=n
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- CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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build_only: true
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arch.interrupt.gen_isr_table.arc:
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arch_allow: arc
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filter: CONFIG_RGF_NUM_BANKS > 1
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extra_configs:
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- CONFIG_ARC_FIRQ_STACK=y
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- CONFIG_TEST_HW_STACK_PROTECTION=n
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arch.interrupt.gen_isr_table.riscv_direct:
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arch_allow:
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- riscv32
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- riscv64
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platform_exclude:
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- m2gl025_miv
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- adp_xc7k_ae350
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filter: CONFIG_RISCV_PRIVILEGED
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extra_configs:
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- CONFIG_GEN_IRQ_VECTOR_TABLE=y
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arch.interrupt.gen_isr_table.riscv_no_direct:
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platform_exclude: m2gl025_miv
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arch_allow:
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- riscv32
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- riscv64
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filter: CONFIG_RISCV_PRIVILEGED
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extra_configs:
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- CONFIG_GEN_IRQ_VECTOR_TABLE=n
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arch.interrupt.gen_isr_table.bit_shift_2nd_level:
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platform_allow: qemu_riscv32
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filter: CONFIG_RISCV_PRIVILEGED
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extra_configs:
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- CONFIG_1ST_LEVEL_INTERRUPT_BITS=7
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- CONFIG_2ND_LEVEL_INTERRUPT_BITS=9
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arch.interrupt.gen_isr_table.bit_shift_3rd_level:
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platform_allow: qemu_riscv32
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filter: CONFIG_RISCV_PRIVILEGED
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extra_configs:
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- CONFIG_MULTI_LEVEL_INTERRUPTS=y
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- CONFIG_2ND_LEVEL_INTERRUPTS=y
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- CONFIG_3RD_LEVEL_INTERRUPTS=y
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- CONFIG_1ST_LEVEL_INTERRUPT_BITS=8
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- CONFIG_2ND_LEVEL_INTERRUPT_BITS=11
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- CONFIG_3RD_LEVEL_INTERRUPT_BITS=13
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