0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
39 lines
931 B
C
39 lines
931 B
C
/* cpu.h - automatically selects the correct arch.h file to include */
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/*
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* Copyright (c) 1997-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_CPU_H_
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#include <sys/arch_interface.h>
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#if defined(CONFIG_X86)
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#include <arch/x86/arch.h>
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#elif defined(CONFIG_ARM64)
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#include <arch/arm64/arch.h>
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#elif defined(CONFIG_ARM)
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#include <arch/arm/aarch32/arch.h>
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#elif defined(CONFIG_ARC)
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#include <arch/arc/arch.h>
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#elif defined(CONFIG_NIOS2)
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#include <arch/nios2/arch.h>
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#elif defined(CONFIG_RISCV)
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#include <arch/riscv/arch.h>
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#elif defined(CONFIG_XTENSA)
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#include <arch/xtensa/arch.h>
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#elif defined(CONFIG_MIPS)
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#include <arch/mips/arch.h>
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#elif defined(CONFIG_ARCH_POSIX)
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#include <arch/posix/arch.h>
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#elif defined(CONFIG_SPARC)
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#include <arch/sparc/arch.h>
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#else
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#error "Unknown Architecture"
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_CPU_H_ */
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