Ruud Derwig 0076313bcb soc: arc: Increase cpu frequency for nsim_hs_smp ... 0.5 Mhz with 100 ticks per sec leaves 5000 cycles per tick, which broke some tests that assumed more work within 1 tick. Set to 1 Mhz: balance multi-core simulation speed and tick duration. Fixes #27943 Signed-off-by: Ruud Derwig <Ruud.Derwig@synopsys.com>		2020-09-16 14:35:31 -05:00
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snps_arc_hsdk	device: Const-ify all device driver instance pointers	2020-09-02 13:48:13 +02:00
snps_arc_iot	device: Const-ify all device driver instance pointers	2020-09-02 13:48:13 +02:00
snps_emsdp	boards: arc: emsdp: fix secure config for emsdp_em7d_esp	2020-06-09 11:30:37 +02:00
snps_emsk	device: Const-ify all device driver instance pointers	2020-09-02 13:48:13 +02:00
snps_nsim	soc: arc: Increase cpu frequency for nsim_hs_smp	2020-09-16 14:35:31 -05:00
snps_qemu	ARC: Add support for basic QEMU platform for ARC EM & HS	2020-06-08 16:58:37 -04:00