391935bea1
This had been hacked into the linker script, define a proper MEMORY region for it. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
82 lines
2.7 KiB
Plaintext
82 lines
2.7 KiB
Plaintext
/*
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* Copyright (c) 2011-2014, Wind River Systems, Inc.
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* Copyright (c) 2019-2020 Intel Corp.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Directives for linker MEMORY regions for all x86
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*
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* By default, the kernel is linked at its physical address and all addresses
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* are in RAM.
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*
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* If CONFIG_XIP is enabled, then another MEMORY region is declared for ROM,
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* and this is where the Zephyr image is booted from. The linker LMAs and VMAs
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* are set up, such that read/write data/bss have their VMA addresses
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* in RAM and are copied from flash at boot. Text/rodata linked in-place in
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* flash.
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*/
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#ifndef ARCH_X86_MEMORY_LD
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#define ARCH_X86_MEMORY_LD
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#include <autoconf.h>
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#include <devicetree.h>
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/* Bounds of physical RAM from DTS */
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#define PHYS_RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
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#define PHYS_RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
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#define KERNEL_BASE_ADDR (PHYS_RAM_ADDR + CONFIG_X86_KERNEL_OFFSET)
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#define KERNEL_RAM_SIZE (PHYS_RAM_SIZE - CONFIG_X86_KERNEL_OFFSET)
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#ifdef CONFIG_XIP
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/* "ROM" is flash, we leave rodata and text there and just copy in data.
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* Board-level DTS must specify a flash region that doesn't overlap with
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* sram0, so that DT_PHYS_LOAD_ADDR is set.
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*/
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#define FLASH_ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
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#define PHYS_LOAD_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
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#endif
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#ifdef CONFIG_X86_64
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/* Locore must be addressable by real mode and so cannot extend past 64K.
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* Skip reserved stuff in the first page
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*/
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#define LOCORE_BASE 0x1000
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#define LOCORE_SIZE (0x10000 - LOCORE_BASE)
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#endif
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MEMORY
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{
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#if defined(CONFIG_XIP)
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/* Address range where the kernel will be installed on a flash part (XIP),
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* or copied into physical RAM by a loader (MMU)
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*/
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ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = FLASH_ROM_SIZE
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#endif
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/* Linear address range to link the kernel. If non-XIP, everything is
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* linked in this space. Otherwise, rodata and text are linked at their
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* physical ROM locations
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*/
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RAM (wx) : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
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#ifdef CONFIG_X86_64
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/* Special low-memory area for bootstrapping other CPUs from real mode */
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LOCORE (wx) : ORIGIN = LOCORE_BASE, LENGTH = LOCORE_SIZE
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#else
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/*
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* On 32-bit x86, fake memory area for build-time IDT generation data.
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* 64-bit doesn't use this, interrupts are all manaaged at runtime.
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*
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* It doesn't matter where this region goes as it is stripped from the
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* final ELF image. The address doesn't even have to be valid on the
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* target. However, it shouldn't overlap any other regions.
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*/
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IDT_LIST : ORIGIN = 0xFFFF1000, LENGTH = 2K
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#endif /* !CONFIG_X86_64 */
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}
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#endif /* ARCH_X86_MEMORY_LD */
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