38e17b68e3
The x86 paging code has been rewritten to support another paging mode and non-identity virtual mappings. - Paging code now uses an array of paging level characteristics and walks tables using for loops. This is opposed to having different functions for every paging level and lots of #ifdefs. The code is now more concise and adding new paging modes should be trivial. - We now support 32-bit, PAE, and IA-32e page tables. - The page tables created by gen_mmu.py are now installed at early boot. There are no longer separate "flat" page tables. These tables are mutable at any time. - The x86_mmu code now has a private header. Many definitions that did not need to be in public scope have been moved out of mmustructs.h and either placed in the C file or in the private header. - Improvements to dumping page table information, with the physical mapping and flags all shown - arch_mem_map() implemented - x86 userspace/memory domain code ported to use the new infrastructure. - add logic for physical -> virtual instruction pointer transition, including cleaning up identity mappings after this takes place. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
156 lines
3.9 KiB
C
156 lines
3.9 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_THREAD_H_
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#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_THREAD_H_
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#define X86_THREAD_FLAG_ALL 0x01 /* _thread_arch.flags: entire state saved */
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/*
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* GDT selectors - these must agree with the GDT layout in locore.S.
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*/
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#define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
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#define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
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#define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
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#define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
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#define X86_USER_CS_32 0x28 /* 32-bit user data (unused) */
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#define X86_USER_DS 0x30 /* 64-bit user mode data */
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#define X86_USER_CS 0x38 /* 64-bit user mode code */
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/* Value programmed into bits 63:32 of STAR MSR with proper segment
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* descriptors for implementing user mode with syscall/sysret
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*/
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#define X86_STAR_UPPER ((X86_USER_CS_32 << 16) | X86_KERNEL_CS)
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#define X86_KERNEL_CPU0_TR 0x40 /* 64-bit task state segment */
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#define X86_KERNEL_CPU1_TR 0x50 /* 64-bit task state segment */
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#define X86_KERNEL_CPU2_TR 0x60 /* 64-bit task state segment */
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#define X86_KERNEL_CPU3_TR 0x70 /* 64-bit task state segment */
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/*
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* Some SSE definitions. Ideally these will ultimately be shared with 32-bit.
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*/
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#define X86_FXSAVE_SIZE 512 /* size and alignment of buffer ... */
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#define X86_FXSAVE_ALIGN 16 /* ... for FXSAVE/FXRSTOR ops */
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#define X86_MXCSR_SANE 0x1dc0 /* enable division-by-zero exception */
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <arch/x86/mmustructs.h>
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/*
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* 64-bit Task State Segment. One defined per CPU.
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*/
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struct x86_tss64 {
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/*
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* Architecturally-defined portion. It is somewhat tedious to
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* enumerate each member specifically (rather than using arrays)
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* but we need to get (some of) their offsets from assembly.
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*/
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uint8_t reserved0[4];
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uint64_t rsp0; /* privileged stacks */
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uint64_t rsp1;
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uint64_t rsp2;
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uint8_t reserved[8];
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uint64_t ist1; /* interrupt stacks */
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uint64_t ist2;
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uint64_t ist3;
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uint64_t ist4;
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uint64_t ist5;
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uint64_t ist6;
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uint64_t ist7;
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uint8_t reserved1[10];
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uint16_t iomapb; /* offset to I/O base */
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/*
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* Zephyr specific portion. Stash per-CPU data here for convenience.
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*/
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struct _cpu *cpu;
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#ifdef CONFIG_USERSPACE
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/* Privilege mode stack pointer value when doing a system call */
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char *psp;
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/* Storage area for user mode stack pointer when doing a syscall */
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char *usp;
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#endif /* CONFIG_USERSPACE */
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} __packed __aligned(8);
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typedef struct x86_tss64 x86_tss64_t;
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/*
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* The _callee_saved registers are unconditionally saved/restored across
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* context switches; the _thread_arch registers are only preserved when
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* the thread is interrupted. _arch_thread.flags tells __resume when to
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* cheat and only restore the first set. For more details see locore.S.
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*/
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struct _callee_saved {
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uint64_t rsp;
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uint64_t rbx;
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uint64_t rbp;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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uint64_t rip;
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uint64_t rflags;
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};
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typedef struct _callee_saved _callee_saved_t;
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struct _thread_arch {
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uint8_t flags;
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#ifdef CONFIG_USERSPACE
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/* Physical address to page tables used by this thread. Supervisor
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* threads always use the kernel's page table, user thread use
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* per-thread tables stored in the stack object
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*/
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uintptr_t ptables;
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/* Track available unused space in the stack object used for building
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* thread-specific page tables.
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*/
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uint8_t *mmu_pos;
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/* Initial privilege mode stack pointer when doing a system call.
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* Un-set for supervisor threads.
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*/
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char *psp;
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/* SS and CS selectors for this thread when restoring context */
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uint64_t ss;
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uint64_t cs;
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#endif
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uint64_t rax;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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char __aligned(X86_FXSAVE_ALIGN) sse[X86_FXSAVE_SIZE];
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_THREAD_H_ */
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