ef224ce1cd
Make the assembly codes compatible with both GNU and Metaware toolchain. * replace ".balign" with ".align" ".align" assembler directive is supposed by all ARC toolchains and it is implemented in a same way across ARC toolchains. * replace "mov_s __certain_reg" with "mov __certain_reg" Even though GCC encodes those mnemonics and even real HW executes them according to PRM these are restricted ones for mov_s and CCAC rightfully refuses to accept such mnemonics. So for compatibility and clarity sake we switch to 32-bit mov instruction which allows use of all those instructions. * Add "%%" prefix while accessing registers from inline ASM as it is required by MWDT. * Drop "@" prefix while accessing symbols (defined in C code) from ASM code as it is required by MWDT. Signed-off-by: Wayne Ren <wei.ren@synopsys.com> /#
190 lines
3.3 KiB
C
190 lines
3.3 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_
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#define ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_
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#ifndef _ASMLANGUAGE
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#include <toolchain.h>
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#include <sys/sys_io.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <zephyr/types.h>
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#include <stddef.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Implementation of sys_io.h's documented functions */
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static ALWAYS_INLINE
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void sys_out8(uint8_t data, io_port_t port)
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{
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z_arc_v2_aux_reg_write(port, data);
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}
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static ALWAYS_INLINE
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uint8_t sys_in8(io_port_t port)
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{
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return (uint8_t)(z_arc_v2_aux_reg_read(port) & 0x000000ff);
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}
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static ALWAYS_INLINE
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void sys_out16(uint16_t data, io_port_t port)
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{
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z_arc_v2_aux_reg_write(port, data);
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}
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static ALWAYS_INLINE
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uint16_t sys_in16(io_port_t port)
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{
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return (uint16_t)(z_arc_v2_aux_reg_read(port) & 0x0000ffff);
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}
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static ALWAYS_INLINE
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void sys_out32(uint32_t data, io_port_t port)
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{
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z_arc_v2_aux_reg_write(port, data);
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}
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static ALWAYS_INLINE
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uint32_t sys_in32(io_port_t port)
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{
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return z_arc_v2_aux_reg_read(port);
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}
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static ALWAYS_INLINE
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void sys_io_set_bit(io_port_t port, unsigned int bit)
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{
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uint32_t reg = 0;
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__asm__ volatile("lr %1, [%0]\n"
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"bset %1, %1, %2\n"
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"sr %1, [%0];\n\t"
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:
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: "ir" (port),
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"r" (reg), "ir" (bit)
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: "memory", "cc");
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}
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static ALWAYS_INLINE
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void sys_io_clear_bit(io_port_t port, unsigned int bit)
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{
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uint32_t reg = 0;
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__asm__ volatile("lr %1, [%0]\n"
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"bclr %1, %1, %2\n"
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"sr %1, [%0];\n\t"
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:
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: "ir" (port),
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"r" (reg), "ir" (bit)
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: "memory", "cc");
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}
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static ALWAYS_INLINE
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int sys_io_test_bit(io_port_t port, unsigned int bit)
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{
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uint32_t status = _ARC_V2_STATUS32;
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uint32_t reg = 0;
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uint32_t ret;
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__asm__ volatile("lr %2, [%1]\n"
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"btst %2, %3\n"
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"lr %0, [%4];\n\t"
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: "=r" (ret)
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: "ir" (port),
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"r" (reg), "ir" (bit), "i" (status)
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: "memory", "cc");
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return !(ret & _ARC_V2_STATUS32_Z);
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}
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static ALWAYS_INLINE
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int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_set_bit(port, bit);
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return ret;
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}
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static ALWAYS_INLINE
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int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
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{
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int ret;
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ret = sys_io_test_bit(port, bit);
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sys_io_clear_bit(port, bit);
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return ret;
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}
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static ALWAYS_INLINE uint8_t sys_read8(mem_addr_t addr)
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{
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uint8_t value;
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compiler_barrier();
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value = *(volatile uint8_t *)addr;
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compiler_barrier();
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return value;
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}
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static ALWAYS_INLINE void sys_write8(uint8_t data, mem_addr_t addr)
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{
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compiler_barrier();
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*(volatile uint8_t *)addr = data;
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compiler_barrier();
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}
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static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr)
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{
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uint16_t value;
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compiler_barrier();
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value = *(volatile uint16_t *)addr;
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compiler_barrier();
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return value;
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}
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static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr)
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{
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compiler_barrier();
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*(volatile uint16_t *)addr = data;
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compiler_barrier();
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}
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static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
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{
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uint16_t value;
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compiler_barrier();
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value = *(volatile uint32_t *)addr;
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compiler_barrier();
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return value;
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}
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static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
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{
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compiler_barrier();
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*(volatile uint32_t *)addr = data;
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compiler_barrier();
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_ */
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