zephyr/arch/xtensa/core
Anas Nashif 6e27478c3d benchmarking: remove execution benchmarking code
This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.

For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.

Furthermore, much of the assembly code used had issues.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
..
offsets headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
startup Revert "arch: xtensa: Use reset-vector.S in booloader code" 2020-02-08 10:01:24 +02:00
atomic.S kernel: add APIs for atomic os on pointers 2020-03-10 10:18:16 -04:00
CMakeLists.txt arch: xtensa: Add support for Intel Apollolake 2020-02-05 10:43:25 -05:00
cpu_idle.c tracing: move headers under include/tracing 2020-02-07 15:58:05 -05:00
crt1.S xtensa: add calling entry point for multi-processing 2020-03-25 19:07:28 -04:00
fatal.c xtensa: add support to build HAL as part of build process 2019-12-18 20:24:18 -05:00
irq_manage.c arch: Apply dynamic IRQ API change 2020-09-02 13:48:13 +02:00
irq_offload.c isr: Normalize usage of device instance through ISR 2020-09-02 13:48:13 +02:00
window_vectors.S headers: Refactor kernel and arch headers. 2019-11-06 16:07:32 -08:00
xtensa_intgen.py xtensa: xtensa_intgen.py: Change 'not lvl in ...' to 'lvl not in ...' 2019-09-07 07:55:01 -04:00
xtensa_intgen.tmpl
xtensa-asm2-util.S benchmarking: remove execution benchmarking code 2020-09-05 13:28:38 -05:00
xtensa-asm2.c arch: Apply dynamic IRQ API change 2020-09-02 13:48:13 +02:00