2b6c574499
The hardcoded APIC ID will be kept as default if the CPU is not found in ACPI MADT. Note that ACPI may expose more "CPUs" than there actually are physically. Thus, make the logic aware of this possibility by checking the enabled flas. (Non-enabled CPU are ignored). This fixes up_squared board made of Celeron CPU. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
175 lines
4.4 KiB
C
175 lines
4.4 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_arch_data.h>
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#include <kernel_arch_func.h>
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#include <kernel_structs.h>
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#include <kernel_internal.h>
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#include <arch/x86/multiboot.h>
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#include <x86_mmu.h>
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#include <drivers/interrupt_controller/loapic.h>
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#include <arch/x86/acpi.h>
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/*
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* Map of CPU logical IDs to CPU local APIC IDs. By default,
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* we assume this simple identity mapping, as found in QEMU.
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* The symbol is weak so that boards/SoC files can override.
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*/
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__weak uint8_t x86_cpu_loapics[] = { 0, 1, 2, 3 };
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extern char x86_ap_start[]; /* AP entry point in locore.S */
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extern uint8_t _exception_stack[];
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extern uint8_t _exception_stack1[];
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extern uint8_t _exception_stack2[];
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extern uint8_t _exception_stack3[];
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#ifdef CONFIG_X86_KPTI
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extern uint8_t z_x86_trampoline_stack[];
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extern uint8_t z_x86_trampoline_stack1[];
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extern uint8_t z_x86_trampoline_stack2[];
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extern uint8_t z_x86_trampoline_stack3[];
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#endif /* CONFIG_X86_KPTI */
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss0 = {
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#ifdef CONFIG_X86_KPTI
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.ist2 = (uint64_t) z_x86_trampoline_stack + Z_X86_TRAMPOLINE_STACK_SIZE,
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#endif
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.ist7 = (uint64_t) _exception_stack + CONFIG_X86_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[0])
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};
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#if CONFIG_MP_NUM_CPUS > 1
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss1 = {
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#ifdef CONFIG_X86_KPTI
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.ist2 = (uint64_t) z_x86_trampoline_stack1 + Z_X86_TRAMPOLINE_STACK_SIZE,
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#endif
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.ist7 = (uint64_t) _exception_stack1 + CONFIG_X86_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[1])
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};
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#endif
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#if CONFIG_MP_NUM_CPUS > 2
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss2 = {
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#ifdef CONFIG_X86_KPTI
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.ist2 = (uint64_t) z_x86_trampoline_stack2 + Z_X86_TRAMPOLINE_STACK_SIZE,
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#endif
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.ist7 = (uint64_t) _exception_stack2 + CONFIG_X86_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[2])
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};
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#endif
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#if CONFIG_MP_NUM_CPUS > 3
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Z_GENERIC_SECTION(.tss)
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struct x86_tss64 tss3 = {
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#ifdef CONFIG_X86_KPTI
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.ist2 = (uint64_t) z_x86_trampoline_stack3 + Z_X86_TRAMPOLINE_STACK_SIZE,
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#endif
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.ist7 = (uint64_t) _exception_stack3 + CONFIG_X86_EXCEPTION_STACK_SIZE,
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.iomapb = 0xFFFF,
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.cpu = &(_kernel.cpus[3])
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};
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#endif
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struct x86_cpuboot x86_cpuboot[] = {
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{
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.tr = X86_KERNEL_CPU0_TR,
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.gs_base = &tss0,
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.sp = (uint64_t) z_interrupt_stacks[0] +
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Z_KERNEL_STACK_SIZE_ADJUST(CONFIG_ISR_STACK_SIZE),
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.stack_size =
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Z_KERNEL_STACK_SIZE_ADJUST(CONFIG_ISR_STACK_SIZE),
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.fn = z_x86_prep_c,
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},
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#if CONFIG_MP_NUM_CPUS > 1
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{
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.tr = X86_KERNEL_CPU1_TR,
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.gs_base = &tss1
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},
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#endif
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#if CONFIG_MP_NUM_CPUS > 2
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{
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.tr = X86_KERNEL_CPU2_TR,
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.gs_base = &tss2
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},
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#endif
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#if CONFIG_MP_NUM_CPUS > 3
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{
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.tr = X86_KERNEL_CPU3_TR,
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.gs_base = &tss3
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},
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#endif
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};
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/*
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* Send the INIT/STARTUP IPI sequence required to start up CPU 'cpu_num', which
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* will enter the kernel at fn(arg), running on the specified stack.
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*/
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void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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arch_cpustart_t fn, void *arg)
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{
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uint8_t vector = ((unsigned long) x86_ap_start) >> 12;
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uint8_t apic_id;
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if (IS_ENABLED(CONFIG_ACPI)) {
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struct acpi_cpu *cpu;
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cpu = z_acpi_get_cpu(cpu_num);
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if (cpu != NULL) {
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/* We update the apic_id, x86_ap_start will need it. */
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x86_cpu_loapics[cpu_num] = cpu->apic_id;
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}
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}
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apic_id = x86_cpu_loapics[cpu_num];
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x86_cpuboot[cpu_num].sp = (uint64_t) Z_KERNEL_STACK_BUFFER(stack) + sz;
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x86_cpuboot[cpu_num].stack_size = sz;
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x86_cpuboot[cpu_num].fn = fn;
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x86_cpuboot[cpu_num].arg = arg;
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z_loapic_ipi(apic_id, LOAPIC_ICR_IPI_INIT, 0);
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k_busy_wait(10000);
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z_loapic_ipi(apic_id, LOAPIC_ICR_IPI_STARTUP, vector);
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while (x86_cpuboot[cpu_num].ready == 0) {
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}
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}
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/* Per-CPU initialization, C domain. On the first CPU, z_x86_prep_c is the
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* next step. For other CPUs it is probably smp_init_top().
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*/
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FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot)
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{
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x86_sse_init(NULL);
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/* The internal cpu_number is the index to x86_cpuboot[] */
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z_loapic_enable((unsigned char)(cpuboot - x86_cpuboot));
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#ifdef CONFIG_USERSPACE
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/* Set landing site for 'syscall' instruction */
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z_x86_msr_write(X86_LSTAR_MSR, (uint64_t)z_x86_syscall_entry_stub);
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/* Set segment descriptors for syscall privilege transitions */
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z_x86_msr_write(X86_STAR_MSR, (uint64_t)X86_STAR_UPPER << 32);
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/* Mask applied to RFLAGS when making a syscall */
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z_x86_msr_write(X86_FMASK_MSR, EFLAGS_SYSCALL);
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#endif
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/* Enter kernel, never return */
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cpuboot->ready++;
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cpuboot->fn(cpuboot->arg);
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}
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