d31ee53b60
This adds a new kconfig and corresponding code to allow flushing auto-refill data TLBs when page tables are swapped (e.g. during context switching). This is mainly used to avoid multi-hit TLB exception raised by certain memory access pattern. If memory is only marked for user mode access but not inside a memory domain, accessing that page in kernel mode would result in a TLB being filled with kernel ASID. When going back into user mode, access to the memory would result in another TLB being filled with the user mode ASID. Now there are two entries on the same memory page, and the multi-hit TLB exception will be raised if that memory page is accessed. This type of access is better served using memory partition and memory domain to share data. However, this type of access is not prohibited but highly discouraged. Wrapping the code in kconfig is simply because of the execution penalty as there will be unnecessary TLB refilling being done. So only enable this if necessary. Fixes #88772 Signed-off-by: Daniel Leung <daniel.leung@intel.com> |
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| .. | ||
| offsets | ||
| startup | ||
| CMakeLists.txt | ||
| coredump.c | ||
| cpu_idle.c | ||
| crt1.S | ||
| debug_helpers_asm.S | ||
| elf.c | ||
| fatal.c | ||
| gdbstub.c | ||
| gen_vectors.py | ||
| gen_zsr.py | ||
| irq_manage.c | ||
| irq_offload.c | ||
| mem_manage.c | ||
| mmu.c | ||
| mpu.c | ||
| prep_c.c | ||
| ptables.c | ||
| README_MMU.txt | ||
| README_WINDOWS.rst | ||
| smp.c | ||
| syscall_helper.c | ||
| thread.c | ||
| timing.c | ||
| tls.c | ||
| userspace.S | ||
| vector_handlers.c | ||
| window_vectors.S | ||
| xcc_stubs.c | ||
| xtensa_asm2_util.S | ||
| xtensa_backtrace.c | ||
| xtensa_hifi.S | ||
| xtensa_intgen.py | ||
| xtensa_intgen.tmpl | ||