Correct management of I2C write transfers that are driven from 2
I2C messages, one for the transfer of the address to write
to and a following message for the transfer of the data to be written.
In this case, no START and STOP bit should be triggered between the 2
I2C transfers.
In STM32 I2C v1 driver, this simply means not emitting a START
condition when the input sequence does not set the RESTART flag.
In STM32 I2C v2 driver, this can only be achieved using the SoC I2C
controller Reload Mode feature, hence update Reload Mode implementation
to use reload mode for both transfers over 255 bytes (splitted in
chunks) and for cases where no STOP and START bits are emitted between
2 transfer in the same transaction.
Regarding STM32 I2C v2 driver, the reload mode must be enable before the
first transaction, known that it's needed due to the following
transaction. Therefore we need to parse the messages grouped in the same
transaction to detect such sequences (a message without STOP flag
followed by a message without RESTART flag) and when so, pass the
information to the I2C driver through RTIO framework. To achieve that,
let's use a free bit from I2C message flags (bit 7) in the message
for which we need to enable SoC ReloadMode from the first transfer.
We check that this bit flag is not used by the I2C framework prior
using it.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
5740dfe77b