abbd19c393
Selection of these GIC Kconfigs have been deprecated for more than 2 releases, users should use the devicetree method instead, update the Kconfigs. The SOCs below have been updated to not select `GIC_V3`, since their devicetree already have the required compatible: - fvp_aemv8r - rzt2m - rk3658 Signed-off-by: Yong Cong Sin <ycsin@meta.com>
67 lines
1.7 KiB
Plaintext
67 lines
1.7 KiB
Plaintext
# ARM Generic Interrupt Controller (GIC) configuration
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# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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# SPDX-License-Identifier: Apache-2.0
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if CPU_CORTEX
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config GIC
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bool
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config GIC_V1
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def_bool DT_HAS_ARM_GIC_V1_ENABLED
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select GIC
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help
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The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the
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ARM Cortex-family processors.
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config GIC_V2
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def_bool DT_HAS_ARM_GIC_V2_ENABLED
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select GIC
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help
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The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the
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ARM Cortex-family processors.
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config GIC_V3
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def_bool DT_HAS_ARM_GIC_V3_ENABLED
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select GIC
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help
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The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600)
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works with the ARM Cortex-family processors.
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config GIC_VER
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int
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depends on GIC
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default 1 if GIC_V1
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default 2 if GIC_V2
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default 3 if GIC_V3
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config GIC_SINGLE_SECURITY_STATE
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bool
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depends on GIC_V3
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help
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Some ARM Cortex-family processors only supports single security
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state.
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config GIC_V3_RDIST_MATCHING_AFF0_ONLY
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bool
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depends on GIC_V3
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default y if CPU_CORTEX_R52
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help
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Some platforms only use aff0 to match mpdir and GICR.aff. With this
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enabled, we find the target redistributor by comparing the aff0 only.
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config GIC_V3_ITS
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bool "GIC v3 Interrupt Translation Service"
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depends on GIC_V3
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# ITS generates Non-secure Group 1 LPI interrupts, requiring EL1NS
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select ARMV8_A_NS
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select DYNAMIC_INTERRUPTS
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help
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Support for the optional Interrupt Translation Service used to translate
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hardware interrupt from PCIe MSI messages for example. Please note
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that ITS uses dynamic memory, so HEAP_MEM_POOL_SIZE should be
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enough to allocate ITS tables (size is probed at runtime).
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endif # CPU_CORTEX
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