0e6aee3479
Tests that exercise z_xtensa_cache_[flush|inv|flush_inv]_all() functions. These tests are at board level because what is mapped into memory is SoC/board dependent - no one wants side effects due writing to some inappropriate address. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
3 lines
38 B
Plaintext
3 lines
38 B
Plaintext
CONFIG_ZTEST=y
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CONFIG_ZTEST_NEW_API=y
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