zephyr/soc
Enjia Mai a0c64cbbb1 boards: xtensa: Activate the intel_adsp west runner
Make the intel_adsp west runner starting to work on all the
intel_adsp boards. Changes include:

1. Make the cavstool.py work as a service in remote host
   ADSP board and rename it to cavstool_server.py.

2. Active the runner and adds a common board.cmake file to
   specify the default signing key for cavs boards.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-06-05 14:13:57 +02:00
..
arc ARC: boards: allow MWDT toolchain for nsim_hs6x and nsim_hs6x_smp 2022-05-10 14:12:25 -04:00
arm soc: stm32wb: Move MB_MEM2 linker section to SRAM1 2022-05-27 17:46:49 -07:00
arm64 boards: imx8mm: add partial pin control support 2022-05-12 16:57:17 -05:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
riscv ztest: Fix userspace ztests in new API 2022-05-25 11:20:13 +09:00
sparc linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
xtensa boards: xtensa: Activate the intel_adsp west runner 2022-06-05 14:13:57 +02:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00