Tim Lin 14e9e7a814 soc: riscv/riscv-ite: chip_chipregs: add chip register address ... Add register address including external timer and watchdog(ETWD), general control(GCTRL), serial peripheral interface(SPI). Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>		2021-04-23 07:03:10 -04:00
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litex-vexriscv	soc: riscv: litex-vexriscv: change CSR accessors	2020-10-02 11:36:16 +02:00
openisa_rv32m1	riscv: add support for thread local storage	2020-10-24 10:52:00 -07:00
riscv-ite	soc: riscv/riscv-ite: chip_chipregs: add chip register address	2021-04-23 07:03:10 -04:00
riscv-privilege	pinmux: sifive: Convert SiFive pinmux to be devicetree based	2021-02-15 08:33:00 -05:00
CMakeLists.txt