f7ddcd2713
With GCC 11 now supporting low overhead branching in ARMv8.1, ASM "LE" (loop-end) instructions would trigger an INVSTATE hard-fault after FPSCR was set to 0. This was due to the FPSCR getting a new field in ARMv8.1. LTPSIZE is now set to it's reset value of Tail predication not applied. Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com> |
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| .. | ||
| arm_hardfault_validation | ||
| arm_interrupt | ||
| arm_irq_advanced_features | ||
| arm_irq_vector_table | ||
| arm_mem_protect | ||
| arm_no_multithreading | ||
| arm_ramfunc | ||
| arm_runtime_nmi | ||
| arm_sw_vector_relay | ||
| arm_thread_swap | ||
| arm_thread_swap_tz | ||
| arm_tz_wrap_func | ||